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include: sbi: Add mtinst/htinst psuedoinstructions

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Add psuedoinstruction encodings written to mtinst/htinst for faults
caused by implicit memory access for VS-stage address translation

Signed-off-by: dramforever <dramforever@live.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
dramforever
2022-06-09 15:07:29 +08:00
committed by Anup Patel
parent 9dc5ec5c51
commit 551c70c040
1 changed files with 20 additions and 0 deletions
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20
include/sbi/riscv_encoding.h
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@@ -841,6 +841,26 @@
#define INSN_MASK_FENCE_TSO 0xffffffff
#define INSN_MATCH_FENCE_TSO 0x8330000f
#if __riscv_xlen == 64
/* 64-bit read for VS-stage address translation (RV64) */
#define INSN_PSEUDO_VS_LOAD 0x00003000
/* 64-bit write for VS-stage address translation (RV64) */
#define INSN_PSEUDO_VS_STORE 0x00003020
#elif __riscv_xlen == 32
/* 32-bit read for VS-stage address translation (RV32) */
#define INSN_PSEUDO_VS_LOAD 0x00002000
/* 32-bit write for VS-stage address translation (RV32) */
#define INSN_PSEUDO_VS_STORE 0x00002020
#else
#error "Unexpected __riscv_xlen"
#endif
#define INSN_16BIT_MASK 0x3
#define INSN_32BIT_MASK 0x1c