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https://github.com/riscv-software-src/opensbi.git
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lib: fix csr detect support
csr_read_allowed/csr_read_allowed requires trap.case to detect the results, but if no exception occurs, the value of trap.case will remain unchanged, which makes the detection results unreliable. Add code to initialize trap.case to 0. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
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@@ -12,6 +12,7 @@
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_trap.h>
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#define csr_read_allowed(csr_num, trap) \
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({ \
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@@ -19,6 +20,7 @@
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register ulong ttmp asm("a4"); \
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register ulong mtvec = sbi_hart_expected_trap_addr(); \
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register ulong ret = 0; \
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((struct sbi_trap_info *)(trap))->cause = 0; \
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asm volatile( \
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"add %[ttmp], %[tinfo], zero\n" \
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"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \
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@@ -36,6 +38,7 @@
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register ulong tinfo asm("a3") = (ulong)trap; \
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register ulong ttmp asm("a4"); \
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register ulong mtvec = sbi_hart_expected_trap_addr(); \
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((struct sbi_trap_info *)(trap))->cause = 0; \
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asm volatile( \
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"add %[ttmp], %[tinfo], zero\n" \
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"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \
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@@ -406,7 +406,6 @@ __mhpm_skip:
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#undef __check_csr
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/* Detect if hart supports SCOUNTEREN feature */
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trap.cause = 0;
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val = csr_read_allowed(CSR_SCOUNTEREN, (unsigned long)&trap);
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if (!trap.cause) {
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csr_write_allowed(CSR_SCOUNTEREN, (unsigned long)&trap, val);
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@@ -415,7 +414,6 @@ __mhpm_skip:
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}
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/* Detect if hart supports MCOUNTEREN feature */
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trap.cause = 0;
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val = csr_read_allowed(CSR_MCOUNTEREN, (unsigned long)&trap);
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if (!trap.cause) {
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csr_write_allowed(CSR_MCOUNTEREN, (unsigned long)&trap, val);
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@@ -424,7 +422,6 @@ __mhpm_skip:
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}
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/* Detect if hart supports time CSR */
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trap.cause = 0;
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csr_read_allowed(CSR_TIME, (unsigned long)&trap);
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if (!trap.cause)
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hfeatures->features |= SBI_HART_HAS_TIME;
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