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include: sbi: Add TINFO debug trigger CSR

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Add the missing TINFO debug trigger CSR.

Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Himanshu Chauhan
2024-01-09 22:30:14 +05:30
committed by Anup Patel
parent b752099da8
commit 20ca19ab03
1 changed files with 1 additions and 0 deletions
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include/sbi/riscv_encoding.h
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@@ -686,6 +686,7 @@
#define CSR_TDATA1 0x7a1
#define CSR_TDATA2 0x7a2
#define CSR_TDATA3 0x7a3
#define CSR_TINFO 0x7a4
/* Debug Mode Registers */
#define CSR_DCSR 0x7b0