Atish Patra 023aa6bb04 lib: Do not access mi/edeleg register if S mode is not present. ...

As per the RISC-V ISA, mideleg and medeleg registers should not exist
if S-mode is not present for a hart.

We shouldn't access these CSRs if non S-mode harts.

Signed-off-by: Atish Patra <atish.patra@wdc.com>

2019-01-22 10:03:49 +05:30

..

objects.mk

include: Add hard FP access macros and defines

2019-01-03 14:21:08 -08:00

riscv_asm.c

include: Remove redundant csr_read_n() and csr_write_n()

2019-01-02 09:57:12 +05:30

riscv_atomic.c

lib: Add atomic bit set/clear operations.

2019-01-22 10:03:49 +05:30

riscv_hardfp.S

include: Add hard FP access macros and defines

2019-01-03 14:21:08 -08:00

riscv_locks.c

Initial commit.

2018-12-11 19:24:06 +05:30

sbi_console.c

lib: code cleanup

2019-01-21 09:58:33 +05:30

sbi_ecall.c

lib: Move ECALL defines to sbi_ecall_interface.h

2018-12-27 09:29:29 +05:30

sbi_emulate_csr.c

lib: Don't emulate CSR read for misa and mhartid

2018-12-16 10:15:55 +05:30

sbi_hart.c

lib: Do not access mi/edeleg register if S mode is not present.

2019-01-22 10:03:49 +05:30

sbi_illegal_insn.c

lib: Redirect illegal instruction trap to S-mode when not handled

2018-12-31 09:28:26 +05:30

sbi_init.c

lib: Fix banner

2019-01-21 09:58:33 +05:30

sbi_ipi.c

lib: Allow sending IPI to self.

2019-01-22 10:03:49 +05:30

sbi_misaligned_ldst.c

lib: Handle misaligned load/store on FP regs

2019-01-03 14:21:08 -08:00

sbi_system.c

lib: Simplify sbi_platform early_init() and final_init() hooks

2018-12-27 09:35:09 +05:30

sbi_timer.c

lib: Simplify sbi_platform timer_init() hooks

2018-12-27 09:35:09 +05:30

sbi_trap.c

include: Add documentation for sbi_trap_regs and friends

2019-01-16 11:25:25 +05:30