forked from Mirrors/opensbi
eeab500a65
I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC (which is based on Andes AX45MP core) due to this reason IP blocks using DMA will fail. As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. SBI_EXT_ANDES_IOCP_SW_WORKAROUND checks if the IOCP errata should be applied to handle cache management. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
61 lines
1.9 KiB
C
61 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*
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*/
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#include <andes/andes45_pma.h>
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#include <andes/andes_sbi.h>
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#include <platform_override.h>
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#include <sbi/sbi_domain.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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static const struct andes45_pma_region renesas_rzfive_pma_regions[] = {
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{
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.pa = 0x58000000,
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.size = 0x8000000,
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.flags = ANDES45_PMACFG_ETYP_NAPOT |
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ANDES45_PMACFG_MTYP_MEM_NON_CACHE_BUF,
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.dt_populate = true,
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.shared_dma = true,
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.no_map = true,
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.dma_default = true,
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},
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};
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static int renesas_rzfive_final_init(bool cold_boot, const struct fdt_match *match)
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{
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return andes45_pma_setup_regions(renesas_rzfive_pma_regions,
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array_size(renesas_rzfive_pma_regions));
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}
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int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
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{
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/*
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* Renesas RZ/Five RISC-V SoC has Instruction local memory and
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* Data local memory (ILM & DLM) mapped between region 0x30000
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* to 0x4FFFF. When a virtual address falls within this range,
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* the MMU doesn't trigger a page fault; it assumes the virtual
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* address is a physical address which can cause undesired
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* behaviours for statically linked applications/libraries. To
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* avoid this, add the ILM/DLM memory regions to the root domain
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* region of the PMPU with permissions set to 0x0 for S/U modes
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* so that any access to these regions gets blocked and for M-mode
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* we grant full access.
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*/
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return sbi_domain_root_add_memrange(0x30000, 0x20000, 0x1000,
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SBI_DOMAIN_MEMREGION_M_RWX);
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}
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static const struct fdt_match renesas_rzfive_match[] = {
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{ .compatible = "renesas,r9a07g043f01" },
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{ /* sentinel */ }
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};
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const struct platform_override renesas_rzfive = {
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.match_table = renesas_rzfive_match,
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.early_init = renesas_rzfive_early_init,
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.final_init = renesas_rzfive_final_init,
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.vendor_ext_provider = andes_sbi_vendor_ext_provider,
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};
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