forked from Mirrors/opensbi
de446ccf18
This is not used anywhere. Drop it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
140 lines
3.4 KiB
C
140 lines
3.4 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Andes Technology Corporation
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*
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* Authors:
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* Zong Li <zong@andestech.com>
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* Nylon Chen <nylon7@andestech.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_types.h>
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#include "plicsw.h"
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#include "platform.h"
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static u32 plicsw_ipi_hart_count;
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static struct plicsw plicsw_dev[AE350_HART_COUNT];
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static inline void plicsw_claim(void)
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{
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u32 source_hart = current_hartid();
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plicsw_dev[source_hart].source_id =
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readl(plicsw_dev[source_hart].plicsw_claim);
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}
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static inline void plicsw_complete(void)
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{
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u32 source_hart = current_hartid();
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u32 source = plicsw_dev[source_hart].source_id;
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writel(source, plicsw_dev[source_hart].plicsw_claim);
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}
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static inline void plic_sw_pending(u32 target_hart)
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{
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/*
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* The pending array registers are w1s type.
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* IPI pending array mapping as following:
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*
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* Pending array start address: base + 0x1000
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* -------------------------------------
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* | hart 3 | hart 2 | hart 1 | hart 0 |
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* -------------------------------------
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* Each hart X can send IPI to another hart by setting the
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* corresponding bit in hart X own region(see the below).
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*
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* In each hart region:
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* -----------------------------------------------
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* | bit 7 | bit 6 | bit 5 | bit 4 | ... | bit 0 |
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* -----------------------------------------------
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* The bit 7 is used to send IPI to hart 0
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* The bit 6 is used to send IPI to hart 1
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* The bit 5 is used to send IPI to hart 2
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* The bit 4 is used to send IPI to hart 3
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*/
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u32 source_hart = current_hartid();
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u32 target_offset = (PLICSW_PENDING_PER_HART - 1) - target_hart;
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u32 per_hart_offset = PLICSW_PENDING_PER_HART * source_hart;
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u32 val = 1 << target_offset << per_hart_offset;
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writel(val, plicsw_dev[source_hart].plicsw_pending);
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}
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void plicsw_ipi_send(u32 target_hart)
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{
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if (plicsw_ipi_hart_count <= target_hart)
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return;
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/* Set PLICSW IPI */
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plic_sw_pending(target_hart);
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}
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void plicsw_ipi_clear(u32 target_hart)
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{
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if (plicsw_ipi_hart_count <= target_hart)
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return;
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/* Clear PLICSW IPI */
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plicsw_claim();
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plicsw_complete();
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}
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int plicsw_warm_ipi_init(void)
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{
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u32 hartid = current_hartid();
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if (!plicsw_dev[hartid].plicsw_pending
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&& !plicsw_dev[hartid].plicsw_enable
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&& !plicsw_dev[hartid].plicsw_claim)
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return -1;
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/* Clear PLICSW IPI */
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plicsw_ipi_clear(hartid);
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return 0;
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}
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int plicsw_cold_ipi_init(unsigned long base, u32 hart_count)
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{
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/* Setup source priority */
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uint32_t *priority = (void *)base + PLICSW_PRIORITY_BASE;
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for (int i = 0; i < AE350_HART_COUNT * PLICSW_PENDING_PER_HART; i++)
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writel(1, &priority[i]);
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/* Setup target enable */
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uint32_t enable_mask = PLICSW_HART_MASK;
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for (int i = 0; i < AE350_HART_COUNT; i++) {
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uint32_t *enable = (void *)base + PLICSW_ENABLE_BASE
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+ PLICSW_ENABLE_PER_HART * i;
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writel(enable_mask, &enable[0]);
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enable_mask >>= 1;
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}
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/* Figure-out PLICSW IPI register address */
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plicsw_ipi_hart_count = hart_count;
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for (u32 hartid = 0; hartid < AE350_HART_COUNT; hartid++) {
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plicsw_dev[hartid].source_id = 0;
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plicsw_dev[hartid].plicsw_pending =
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(void *)base
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+ PLICSW_PENDING_BASE
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+ ((hartid / 4) * 4);
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plicsw_dev[hartid].plicsw_enable =
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(void *)base
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+ PLICSW_ENABLE_BASE
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+ PLICSW_ENABLE_PER_HART * hartid;
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plicsw_dev[hartid].plicsw_claim =
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(void *)base
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+ PLICSW_CONTEXT_BASE
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+ PLICSW_CONTEXT_CLAIM
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+ PLICSW_CONTEXT_PER_HART * hartid;
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}
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return 0;
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}
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