forked from Mirrors/opensbi
ce7c490719
Move Andes PLICSW ipi device to fdt ipi framework, this patch is based
on Leo's modified IPI scheme on PLICSW.
Current IPI scheme uses bit 0 of pending reigster on PLICSW to send IPI
from hart 0 to hart 7, but bit 0 needs to be hardwired to 0 according
to spec. After some investigation, self-IPI seems to be seldom or never
used, so we re-order the IPI scheme to support 8 core platforms.
dts example (Quad-core AX45MP):
plicsw: interrupt-controller@e6400000 {
compatible = "andestech,plicsw";
reg = <0x00000000 0xe6400000 0x00000000 0x00400000>;
interrupts-extended = <&CPU0_intc 3
&CPU1_intc 3
&CPU2_intc 3
&CPU3_intc 3>;
interrupt-controller;
#address-cells = <2>;
#interrupt-cells = <2>;
};
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
161 lines
3.8 KiB
C
161 lines
3.8 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Andes Technology Corporation
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*
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* Authors:
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* Zong Li <zong@andestech.com>
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* Nylon Chen <nylon7@andestech.com>
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* Yu Chien Peter Lin <peterlin@andestech.com>
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*/
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#include <libfdt.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_hartmask.h>
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#include <sbi/sbi_ipi.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_string.h>
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#include <sbi/sbi_trap.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/fdt/fdt_fixup.h>
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#include <sbi_utils/irqchip/fdt_irqchip.h>
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#include <sbi_utils/reset/fdt_reset.h>
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#include <sbi_utils/serial/fdt_serial.h>
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#include <sbi_utils/timer/fdt_timer.h>
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#include <sbi_utils/ipi/fdt_ipi.h>
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#include "platform.h"
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#include "cache.h"
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struct sbi_platform platform;
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unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
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unsigned long arg2, unsigned long arg3,
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unsigned long arg4)
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{
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const char *model;
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void *fdt = (void *)arg1;
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u32 hartid, hart_count = 0;
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int rc, root_offset, cpus_offset, cpu_offset, len;
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root_offset = fdt_path_offset(fdt, "/");
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if (root_offset < 0)
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goto fail;
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model = fdt_getprop(fdt, root_offset, "model", &len);
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if (model)
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sbi_strncpy(platform.name, model, sizeof(platform.name) - 1);
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cpus_offset = fdt_path_offset(fdt, "/cpus");
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if (cpus_offset < 0)
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goto fail;
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fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {
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rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
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if (rc)
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continue;
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if (SBI_HARTMASK_MAX_BITS <= hartid)
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continue;
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hart_count++;
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}
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platform.hart_count = hart_count;
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/* Return original FDT pointer */
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return arg1;
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fail:
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while (1)
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wfi();
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}
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/* Platform final initialization. */
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static int ae350_final_init(bool cold_boot)
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{
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void *fdt;
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if (!cold_boot)
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return 0;
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fdt_reset_init();
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fdt = fdt_get_address();
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fdt_fixups(fdt);
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return 0;
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}
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/* Vendor-Specific SBI handler */
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static int ae350_vendor_ext_provider(long extid, long funcid,
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const struct sbi_trap_regs *regs, unsigned long *out_value,
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struct sbi_trap_info *out_trap)
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{
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int ret = 0;
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switch (funcid) {
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case SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS:
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*out_value = csr_read(CSR_MCACHECTL);
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break;
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case SBI_EXT_ANDES_GET_MMISC_CTL_STATUS:
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*out_value = csr_read(CSR_MMISCCTL);
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break;
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case SBI_EXT_ANDES_SET_MCACHE_CTL:
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ret = mcall_set_mcache_ctl(regs->a0);
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break;
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case SBI_EXT_ANDES_SET_MMISC_CTL:
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ret = mcall_set_mmisc_ctl(regs->a0);
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break;
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case SBI_EXT_ANDES_ICACHE_OP:
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ret = mcall_icache_op(regs->a0);
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break;
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case SBI_EXT_ANDES_DCACHE_OP:
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ret = mcall_dcache_op(regs->a0);
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break;
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case SBI_EXT_ANDES_L1CACHE_I_PREFETCH:
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ret = mcall_l1_cache_i_prefetch_op(regs->a0);
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break;
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case SBI_EXT_ANDES_L1CACHE_D_PREFETCH:
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ret = mcall_l1_cache_d_prefetch_op(regs->a0);
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break;
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case SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE:
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ret = mcall_non_blocking_load_store(regs->a0);
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break;
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case SBI_EXT_ANDES_WRITE_AROUND:
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ret = mcall_write_around(regs->a0);
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break;
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default:
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sbi_printf("Unsupported vendor sbi call : %ld\n", funcid);
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asm volatile("ebreak");
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}
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return ret;
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}
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/* Platform descriptor. */
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const struct sbi_platform_operations platform_ops = {
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.final_init = ae350_final_init,
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.console_init = fdt_serial_init,
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.irqchip_init = fdt_irqchip_init,
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.ipi_init = fdt_ipi_init,
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.timer_init = fdt_timer_init,
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.vendor_ext_provider = ae350_vendor_ext_provider
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};
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struct sbi_platform platform = {
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.opensbi_version = OPENSBI_VERSION,
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.platform_version =
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SBI_PLATFORM_VERSION(CONFIG_PLATFORM_ANDES_AE350_MAJOR_VER,
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CONFIG_PLATFORM_ANDES_AE350_MINOR_VER),
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.name = CONFIG_PLATFORM_ANDES_AE350_NAME,
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.features = SBI_PLATFORM_DEFAULT_FEATURES,
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.hart_count = SBI_HARTMASK_MAX_BITS,
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.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
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.platform_ops_addr = (unsigned long)&platform_ops
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};
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