forked from Mirrors/opensbi

Now that all of the overrides are modifying generic_platform_ops directly, remove the unused hooks and forwarding functions. The remaining members of struct platform_override match struct fdt_driver, so use that type instead. This allows a future commit to reuse the fdt_driver-based init function. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-8-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
236 lines
5.8 KiB
C
236 lines
5.8 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Samuel Holland <samuel@sholland.org>
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*/
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#include <platform_override.h>
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#include <thead/c9xx_encoding.h>
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#include <thead/c9xx_pmu.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_ecall_interface.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hsm.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_pmu.h>
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#include <sbi/sbi_scratch.h>
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#include <sbi_utils/fdt/fdt_fixup.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/irqchip/plic.h>
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#define SUN20I_D1_CCU_BASE ((void *)0x02001000)
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#define SUN20I_D1_RISCV_CFG_BASE ((void *)0x06010000)
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#define SUN20I_D1_PPU_BASE ((void *)0x07001000)
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#define SUN20I_D1_PRCM_BASE ((void *)0x07010000)
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/*
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* CCU
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*/
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#define CCU_BGR_ENABLE (BIT(16) | BIT(0))
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#define RISCV_CFG_BGR_REG 0xd0c
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#define PPU_BGR_REG 0x1ac
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static unsigned long csr_mxstatus;
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static unsigned long csr_mhcr;
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static unsigned long csr_mhint;
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static void sun20i_d1_csr_save(void)
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{
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/* Save custom CSRs. */
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csr_mxstatus = csr_read(THEAD_C9XX_CSR_MXSTATUS);
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csr_mhcr = csr_read(THEAD_C9XX_CSR_MHCR);
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csr_mhint = csr_read(THEAD_C9XX_CSR_MHINT);
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/* Flush and disable caches. */
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csr_write(THEAD_C9XX_CSR_MCOR, 0x22);
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csr_write(THEAD_C9XX_CSR_MHCR, 0x0);
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}
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static void sun20i_d1_csr_restore(void)
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{
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/* Invalidate caches and the branch predictor. */
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csr_write(THEAD_C9XX_CSR_MCOR, 0x70013);
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/* Restore custom CSRs, including the cache state. */
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csr_write(THEAD_C9XX_CSR_MXSTATUS, csr_mxstatus);
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csr_write(THEAD_C9XX_CSR_MHCR, csr_mhcr);
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csr_write(THEAD_C9XX_CSR_MHINT, csr_mhint);
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}
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/*
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* PPU
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*/
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#define PPU_PD_ACTIVE_CTRL 0x2c
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static void sun20i_d1_ppu_save(void)
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{
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/* Enable MMIO access. Do not assume S-mode leaves the clock enabled. */
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writel_relaxed(CCU_BGR_ENABLE, SUN20I_D1_PRCM_BASE + PPU_BGR_REG);
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/* Activate automatic power-down during the next WFI. */
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writel_relaxed(1, SUN20I_D1_PPU_BASE + PPU_PD_ACTIVE_CTRL);
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}
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static void sun20i_d1_ppu_restore(void)
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{
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/* Disable automatic power-down. */
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writel_relaxed(0, SUN20I_D1_PPU_BASE + PPU_PD_ACTIVE_CTRL);
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}
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/*
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* RISCV_CFG
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*/
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#define RESET_ENTRY_LO_REG 0x0004
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#define RESET_ENTRY_HI_REG 0x0008
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#define WAKEUP_EN_REG 0x0020
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#define WAKEUP_MASK_REG(i) (0x0024 + 4 * (i))
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static void sun20i_d1_riscv_cfg_save(void)
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{
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struct plic_data *plic = plic_get();
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u32 *plic_sie = plic->pm_data;
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/* Enable MMIO access. Do not assume S-mode leaves the clock enabled. */
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writel_relaxed(CCU_BGR_ENABLE, SUN20I_D1_CCU_BASE + RISCV_CFG_BGR_REG);
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/*
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* Copy the SIE bits to the wakeup registers. D1 has 160 "real"
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* interrupt sources, numbered 16-175. These are the ones that map to
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* the wakeup mask registers (the offset is for GIC compatibility). So
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* copying SIE to the wakeup mask needs some bit manipulation.
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*/
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for (int i = 0; i < PLIC_IE_WORDS(plic) - 1; i++)
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writel_relaxed(plic_sie[i] >> 16 | plic_sie[i + 1] << 16,
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SUN20I_D1_RISCV_CFG_BASE + WAKEUP_MASK_REG(i));
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/* Enable PPU wakeup for interrupts. */
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writel_relaxed(1, SUN20I_D1_RISCV_CFG_BASE + WAKEUP_EN_REG);
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}
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static void sun20i_d1_riscv_cfg_restore(void)
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{
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/* Disable PPU wakeup for interrupts. */
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writel_relaxed(0, SUN20I_D1_RISCV_CFG_BASE + WAKEUP_EN_REG);
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}
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static void sun20i_d1_riscv_cfg_init(void)
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{
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u64 entry = sbi_scratch_thishart_ptr()->warmboot_addr;
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/* Enable MMIO access. */
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writel_relaxed(CCU_BGR_ENABLE, SUN20I_D1_CCU_BASE + RISCV_CFG_BGR_REG);
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/* Program the reset entry address. */
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writel_relaxed(entry, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_LO_REG);
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writel_relaxed(entry >> 32, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_HI_REG);
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}
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static int sun20i_d1_hart_suspend(u32 suspend_type, ulong mmode_resume_addr)
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{
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/* Use the generic code for retentive suspend. */
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if (!(suspend_type & SBI_HSM_SUSP_NON_RET_BIT))
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return SBI_ENOTSUPP;
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plic_suspend();
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sun20i_d1_ppu_save();
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sun20i_d1_riscv_cfg_save();
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sun20i_d1_csr_save();
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/*
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* If no interrupt is pending, this will power down the CPU power
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* domain. Otherwise, this will fall through, and the generic HSM
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* code will jump to the resume address.
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*/
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wfi();
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return 0;
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}
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static void sun20i_d1_hart_resume(void)
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{
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sun20i_d1_csr_restore();
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sun20i_d1_riscv_cfg_restore();
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sun20i_d1_ppu_restore();
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plic_resume();
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}
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static const struct sbi_hsm_device sun20i_d1_ppu = {
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.name = "sun20i-d1-ppu",
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.hart_suspend = sun20i_d1_hart_suspend,
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.hart_resume = sun20i_d1_hart_resume,
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};
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static const struct sbi_cpu_idle_state sun20i_d1_cpu_idle_states[] = {
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{
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.name = "cpu-nonretentive",
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.suspend_param = SBI_HSM_SUSPEND_NON_RET_DEFAULT,
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.local_timer_stop = true,
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.entry_latency_us = 40,
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.exit_latency_us = 67,
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.min_residency_us = 1100,
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.wakeup_latency_us = 67,
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},
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{ }
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};
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static int sun20i_d1_final_init(bool cold_boot)
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{
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int rc;
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if (cold_boot) {
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void *fdt = fdt_get_address_rw();
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sun20i_d1_riscv_cfg_init();
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sbi_hsm_set_device(&sun20i_d1_ppu);
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rc = fdt_add_cpu_idle_states(fdt, sun20i_d1_cpu_idle_states);
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if (rc)
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return rc;
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}
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return generic_final_init(cold_boot);
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}
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static int sun20i_d1_extensions_init(struct sbi_hart_features *hfeatures)
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{
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int rc;
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rc = generic_extensions_init(hfeatures);
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if (rc)
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return rc;
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thead_c9xx_register_pmu_device();
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/* auto-detection doesn't work on t-head c9xx cores */
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/* D1 has 29 mhpmevent csrs, but only 3-9,13-17 have valid value */
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hfeatures->mhpm_mask = 0x0003e3f8;
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hfeatures->mhpm_bits = 64;
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return 0;
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}
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static int sun20i_d1_platform_init(const void *fdt, int nodeoff,
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const struct fdt_match *match)
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{
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generic_platform_ops.final_init = sun20i_d1_final_init;
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generic_platform_ops.extensions_init = sun20i_d1_extensions_init;
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return 0;
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}
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static const struct fdt_match sun20i_d1_match[] = {
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{ .compatible = "allwinner,sun20i-d1" },
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{ },
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};
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const struct fdt_driver sun20i_d1 = {
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.match_table = sun20i_d1_match,
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.init = sun20i_d1_platform_init,
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};
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