forked from Mirrors/opensbi
6ffe1bed09
Move the .align directives after switching the section. We want to align the start of the current section, not the end of the previous section. This also obsoletes the misguided workaround of disabling relaxation. Signed-off-by: Andreas Schwab <schwab@suse.de> Reviewed-by: Anup Patel <anup.patel@wdc.com>
89 lines
1.5 KiB
ArmAsm
89 lines
1.5 KiB
ArmAsm
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_encoding.h>
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#define __ASM_STR(x) x
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#if __riscv_xlen == 64
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#define __REG_SEL(a, b) __ASM_STR(a)
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#define RISCV_PTR .dword
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#elif __riscv_xlen == 32
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#define __REG_SEL(a, b) __ASM_STR(b)
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#define RISCV_PTR .word
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#else
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#error "Unexpected __riscv_xlen"
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#endif
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#define REG_L __REG_SEL(ld, lw)
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#define REG_S __REG_SEL(sd, sw)
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.section .entry, "ax", %progbits
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.align 3
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.globl _start
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_start:
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/* Pick one hart to run the main boot sequence */
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la a3, _hart_lottery
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li a2, 1
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amoadd.w a3, a2, (a3)
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bnez a3, _start_hang
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/* Save a0 and a1 */
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la a3, _boot_a0
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REG_S a0, 0(a3)
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la a3, _boot_a1
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REG_S a1, 0(a3)
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/* Zero-out BSS */
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la a4, _bss_start
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la a5, _bss_end
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_bss_zero:
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REG_S zero, (a4)
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add a4, a4, __SIZEOF_POINTER__
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blt a4, a5, _bss_zero
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_start_warm:
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/* Disable and clear all interrupts */
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csrw CSR_SIE, zero
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csrw CSR_SIP, zero
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/* Setup exception vectors */
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la a3, _start_hang
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csrw CSR_STVEC, a3
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/* Setup stack */
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la a3, _payload_end
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li a4, 0x2000
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add sp, a3, a4
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/* Jump to C main */
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la a3, _boot_a0
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REG_L a0, 0(a3)
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la a3, _boot_a1
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REG_L a1, 0(a3)
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call test_main
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/* We don't expect to reach here hence just hang */
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j _start_hang
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.section .entry, "ax", %progbits
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.align 3
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.globl _start_hang
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_start_hang:
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wfi
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j _start_hang
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.section .entry, "ax", %progbits
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.align 3
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_hart_lottery:
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RISCV_PTR 0
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_boot_a0:
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RISCV_PTR 0
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_boot_a1:
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RISCV_PTR 0
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