forked from Mirrors/opensbi
3d8a952737
csr_read_allowed/csr_read_allowed requires trap.case to detect the results, but if no exception occurs, the value of trap.case will remain unchanged, which makes the detection results unreliable. Add code to initialize trap.case to 0. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
54 lines
1.6 KiB
C
54 lines
1.6 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2020 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Atish Patra <atish.patra@wdc.com>
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*/
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#ifndef __SBI_CSR_DETECT__H
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#define __SBI_CSR_DETECT__H
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_trap.h>
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#define csr_read_allowed(csr_num, trap) \
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({ \
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register ulong tinfo asm("a3") = (ulong)trap; \
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register ulong ttmp asm("a4"); \
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register ulong mtvec = sbi_hart_expected_trap_addr(); \
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register ulong ret = 0; \
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((struct sbi_trap_info *)(trap))->cause = 0; \
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asm volatile( \
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"add %[ttmp], %[tinfo], zero\n" \
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"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \
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"csrr %[ret], %[csr]\n" \
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"csrw " STR(CSR_MTVEC) ", %[mtvec]" \
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: [mtvec] "+&r"(mtvec), [tinfo] "+&r"(tinfo), \
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[ttmp] "+&r"(ttmp), [ret] "=&r" (ret) \
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: [csr] "i" (csr_num) \
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: "memory"); \
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ret; \
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}) \
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#define csr_write_allowed(csr_num, trap, value) \
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({ \
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register ulong tinfo asm("a3") = (ulong)trap; \
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register ulong ttmp asm("a4"); \
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register ulong mtvec = sbi_hart_expected_trap_addr(); \
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((struct sbi_trap_info *)(trap))->cause = 0; \
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asm volatile( \
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"add %[ttmp], %[tinfo], zero\n" \
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"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \
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"csrw %[csr], %[val]\n" \
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"csrw " STR(CSR_MTVEC) ", %[mtvec]" \
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: [mtvec] "+&r"(mtvec), \
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[tinfo] "+&r"(tinfo), [ttmp] "+&r"(ttmp) \
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: [csr] "i" (csr_num), [val] "r" (value) \
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: "memory"); \
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}) \
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#endif
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