forked from Mirrors/opensbi

Allwinner D1 contains a "PPU" power domain controller which can automatically power down/up the CPU power domain. This power domain includes the C906 core along with its CLINT and PLIC. This HSM implementation supports non-retentive hart suspend by: 1) Saving/restoring state that is lost during hart suspend, 2) Performing cache maintenance before/after hart suspend, 3) Configuring wakeup sources before hart suspend, and 4) Asking the PPU to power down the hart when it enters WFI. Since this HSM implementation is for a single-core SoC, it does not need to worry about concurrency or saving multiple instances of state. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
211 lines
5.0 KiB
C
211 lines
5.0 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Samuel Holland <samuel@sholland.org>
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*/
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#include <platform_override.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_ecall_interface.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hsm.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/irqchip/fdt_irqchip_plic.h>
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#define SUN20I_D1_CCU_BASE ((void *)0x02001000)
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#define SUN20I_D1_RISCV_CFG_BASE ((void *)0x06010000)
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#define SUN20I_D1_PPU_BASE ((void *)0x07001000)
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#define SUN20I_D1_PRCM_BASE ((void *)0x07010000)
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/*
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* CCU
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*/
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#define CCU_BGR_ENABLE (BIT(16) | BIT(0))
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#define RISCV_CFG_BGR_REG 0xd0c
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#define PPU_BGR_REG 0x1ac
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/*
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* CSRs
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*/
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#define CSR_MXSTATUS 0x7c0
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#define CSR_MHCR 0x7c1
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#define CSR_MCOR 0x7c2
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#define CSR_MHINT 0x7c5
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static unsigned long csr_mxstatus;
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static unsigned long csr_mhcr;
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static unsigned long csr_mhint;
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static void sun20i_d1_csr_save(void)
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{
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/* Save custom CSRs. */
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csr_mxstatus = csr_read(CSR_MXSTATUS);
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csr_mhcr = csr_read(CSR_MHCR);
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csr_mhint = csr_read(CSR_MHINT);
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/* Flush and disable caches. */
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csr_write(CSR_MCOR, 0x22);
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csr_write(CSR_MHCR, 0x0);
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}
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static void sun20i_d1_csr_restore(void)
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{
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/* Invalidate caches and the branch predictor. */
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csr_write(CSR_MCOR, 0x70013);
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/* Restore custom CSRs, including the cache state. */
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csr_write(CSR_MXSTATUS, csr_mxstatus);
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csr_write(CSR_MHCR, csr_mhcr);
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csr_write(CSR_MHINT, csr_mhint);
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}
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/*
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* PLIC
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*/
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#define PLIC_SOURCES 176
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#define PLIC_IE_WORDS ((PLIC_SOURCES + 31) / 32)
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static u8 plic_priority[PLIC_SOURCES];
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static u32 plic_sie[PLIC_IE_WORDS];
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static u32 plic_threshold;
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static void sun20i_d1_plic_save(void)
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{
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fdt_plic_context_save(true, plic_sie, &plic_threshold);
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fdt_plic_priority_save(plic_priority);
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}
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static void sun20i_d1_plic_restore(void)
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{
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thead_plic_restore();
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fdt_plic_priority_restore(plic_priority);
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fdt_plic_context_restore(true, plic_sie, plic_threshold);
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}
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/*
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* PPU
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*/
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#define PPU_PD_ACTIVE_CTRL 0x2c
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static void sun20i_d1_ppu_save(void)
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{
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/* Enable MMIO access. Do not assume S-mode leaves the clock enabled. */
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writel_relaxed(CCU_BGR_ENABLE, SUN20I_D1_PRCM_BASE + PPU_BGR_REG);
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/* Activate automatic power-down during the next WFI. */
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writel_relaxed(1, SUN20I_D1_PPU_BASE + PPU_PD_ACTIVE_CTRL);
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}
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static void sun20i_d1_ppu_restore(void)
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{
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/* Disable automatic power-down. */
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writel_relaxed(0, SUN20I_D1_PPU_BASE + PPU_PD_ACTIVE_CTRL);
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}
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/*
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* RISCV_CFG
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*/
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#define RESET_ENTRY_LO_REG 0x0004
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#define RESET_ENTRY_HI_REG 0x0008
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#define WAKEUP_EN_REG 0x0020
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#define WAKEUP_MASK_REG(i) (0x0024 + 4 * (i))
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static void sun20i_d1_riscv_cfg_save(void)
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{
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/* Enable MMIO access. Do not assume S-mode leaves the clock enabled. */
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writel_relaxed(CCU_BGR_ENABLE, SUN20I_D1_CCU_BASE + RISCV_CFG_BGR_REG);
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/*
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* Copy the SIE bits to the wakeup registers. D1 has 160 "real"
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* interrupt sources, numbered 16-175. These are the ones that map to
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* the wakeup mask registers (the offset is for GIC compatibility). So
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* copying SIE to the wakeup mask needs some bit manipulation.
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*/
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for (int i = 0; i < PLIC_IE_WORDS - 1; i++)
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writel_relaxed(plic_sie[i] >> 16 | plic_sie[i + 1] << 16,
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SUN20I_D1_RISCV_CFG_BASE + WAKEUP_MASK_REG(i));
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/* Enable PPU wakeup for interrupts. */
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writel_relaxed(1, SUN20I_D1_RISCV_CFG_BASE + WAKEUP_EN_REG);
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}
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static void sun20i_d1_riscv_cfg_restore(void)
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{
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/* Disable PPU wakeup for interrupts. */
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writel_relaxed(0, SUN20I_D1_RISCV_CFG_BASE + WAKEUP_EN_REG);
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}
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static void sun20i_d1_riscv_cfg_init(void)
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{
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unsigned long entry = sbi_hartid_to_scratch(0)->warmboot_addr;
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/* Enable MMIO access. */
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writel_relaxed(CCU_BGR_ENABLE, SUN20I_D1_CCU_BASE + RISCV_CFG_BGR_REG);
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/* Program the reset entry address. */
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writel_relaxed((u32)entry, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_LO_REG);
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writel_relaxed((u64)entry >> 32, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_HI_REG);
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}
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static int sun20i_d1_hart_suspend(u32 suspend_type)
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{
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/* Use the generic code for retentive suspend. */
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if (!(suspend_type & SBI_HSM_SUSP_NON_RET_BIT))
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return SBI_ENOTSUPP;
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sun20i_d1_plic_save();
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sun20i_d1_ppu_save();
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sun20i_d1_riscv_cfg_save();
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sun20i_d1_csr_save();
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/*
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* If no interrupt is pending, this will power down the CPU power
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* domain. Otherwise, this will fall through, and the generic HSM
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* code will jump to the resume address.
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*/
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wfi();
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return 0;
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}
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static void sun20i_d1_hart_resume(void)
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{
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sun20i_d1_csr_restore();
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sun20i_d1_riscv_cfg_restore();
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sun20i_d1_ppu_restore();
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sun20i_d1_plic_restore();
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}
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static const struct sbi_hsm_device sun20i_d1_ppu = {
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.name = "sun20i-d1-ppu",
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.hart_suspend = sun20i_d1_hart_suspend,
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.hart_resume = sun20i_d1_hart_resume,
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};
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static int sun20i_d1_final_init(bool cold_boot, const struct fdt_match *match)
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{
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if (cold_boot) {
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sun20i_d1_riscv_cfg_init();
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sbi_hsm_set_device(&sun20i_d1_ppu);
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}
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return 0;
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}
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static const struct fdt_match sun20i_d1_match[] = {
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{ .compatible = "allwinner,sun20i-d1" },
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{ },
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};
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const struct platform_override sun20i_d1 = {
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.match_table = sun20i_d1_match,
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.final_init = sun20i_d1_final_init,
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};
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