forked from Mirrors/opensbi
980290651f
We add AE350 platform specific SBI handler to implement AE350 specific SBI calls. Signed-off-by: Nylon Chen <nylon7@andestech.com> Reviewed-by: Anup Patel <Anup.Patel@wdc.com> Reviewed-by: Atish Patra <Atish.Patra@wdc.com>
78 lines
2.5 KiB
C
78 lines
2.5 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Andes Technology Corporation
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*
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* Authors:
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* Zong Li <zong@andestech.com>
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* Nylon Chen <nylon7@andestech.com>
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*/
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#ifndef _AE350_PLATFORM_H_
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#define _AE350_PLATFORM_H_
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#define AE350_HART_COUNT 4
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#define AE350_PLIC_ADDR 0xe4000000
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#define AE350_PLIC_NUM_SOURCES 71
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#define AE350_PLICSW_ADDR 0xe6400000
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#define AE350_PLMT_ADDR 0xe6000000
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#define AE350_L2C_ADDR 0xe0500000
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#define AE350_UART_ADDR_OFFSET 0x20
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#define AE350_UART_ADDR (0xf0300000 + AE350_UART_ADDR_OFFSET)
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#define AE350_UART_FREQUENCY 19660800
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#define AE350_UART_BAUDRATE 38400
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#define AE350_UART_REG_SHIFT 2
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#define AE350_UART_REG_WIDTH 0
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enum sbi_ext_andes_fid {
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SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS = 0,
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SBI_EXT_ANDES_GET_MMISC_CTL_STATUS,
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SBI_EXT_ANDES_SET_MCACHE_CTL,
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SBI_EXT_ANDES_SET_MMISC_CTL,
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SBI_EXT_ANDES_ICACHE_OP,
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SBI_EXT_ANDES_DCACHE_OP,
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SBI_EXT_ANDES_L1CACHE_I_PREFETCH,
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SBI_EXT_ANDES_L1CACHE_D_PREFETCH,
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SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE,
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SBI_EXT_ANDES_WRITE_AROUND,
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};
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#define V5_MCACHE_CTL_IC_EN_OFFSET 0
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#define V5_MCACHE_CTL_DC_EN_OFFSET 1
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#define V5_MCACHE_CTL_IC_ECCEN_OFFSET 2
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#define V5_MCACHE_CTL_DC_ECCEN_OFFSET 4
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#define V5_MCACHE_CTL_IC_RWECC_OFFSET 6
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#define V5_MCACHE_CTL_DC_RWECC_OFFSET 7
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#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8
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#define V5_MCACHE_CTL_IC_EN (1UL << V5_MCACHE_CTL_IC_EN_OFFSET)
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#define V5_MCACHE_CTL_DC_EN (1UL << V5_MCACHE_CTL_DC_EN_OFFSET)
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#define V5_MCACHE_CTL_IC_RWECC (1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET)
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#define V5_MCACHE_CTL_DC_RWECC (1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET)
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#define V5_MCACHE_CTL_CCTL_SUEN (1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
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#define V5_L2C_CTL_OFFSET 0x8
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#define V5_L2C_CTL_ENABLE_OFFSET 0
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#define V5_L2C_CTL_IPFDPT_OFFSET 3
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#define V5_L2C_CTL_DPFDPT_OFFSET 5
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#define V5_L2C_CTL_TRAMOCTL_OFFSET 8
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#define V5_L2C_CTL_TRAMICTL_OFFSET 10
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#define V5_L2C_CTL_DRAMOCTL_OFFSET 11
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#define V5_L2C_CTL_DRAMICTL_OFFSET 13
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#define V5_L2C_CTL_ENABLE_MASK (1UL << V5_L2C_CTL_ENABLE_OFFSET)
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#define V5_L2C_CTL_IPFDPT_MASK (3UL << V5_L2C_CTL_IPFDPT_OFFSET)
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#define V5_L2C_CTL_DPFDPT_MASK (3UL << V5_L2C_CTL_DPFDPT_OFFSET)
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#define V5_L2C_CTL_TRAMOCTL_MASK (3UL << V5_L2C_CTL_TRAMOCTL_OFFSET)
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#define V5_L2C_CTL_TRAMICTL_MASK (1UL << V5_L2C_CTL_TRAMICTL_OFFSET)
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#define V5_L2C_CTL_DRAMOCTL_MASK (3UL << V5_L2C_CTL_DRAMOCTL_OFFSET)
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#define V5_L2C_CTL_DRAMICTL_MASK (1UL << V5_L2C_CTL_DRAMICTL_OFFSET)
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#endif /* _AE350_PLATFORM_H_ */
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