forked from Mirrors/opensbi
d71150ee70
Since the FDT is not modified during driver initialization, node offsets are just as suitable as phandles for use as identifiers: they are stable and unique. With this change, it is no longer necessary to pass the phandle to the driver init functions, so these init functions now use the same prototype as other kinds of drivers. This matches what is already done for I2C adapters. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
117 lines
2.7 KiB
C
117 lines
2.7 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Starfive
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*
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* Authors:
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* Minda.chen <Minda.chen@starfivetech.com>
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*/
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_heap.h>
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#include <sbi/sbi_console.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/gpio/fdt_gpio.h>
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#define STARFIVE_GPIO_PINS_DEF 64
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#define STARFIVE_GPIO_OUTVAL 0x40
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#define STARFIVE_GPIO_MASK 0xff
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#define STARFIVE_GPIO_REG_SHIFT_MASK 0x3
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#define STARFIVE_GPIO_SHIFT_BITS 0x3
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struct starfive_gpio_chip {
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unsigned long addr;
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struct gpio_chip chip;
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};
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static int starfive_gpio_direction_output(struct gpio_pin *gp, int value)
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{
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u32 val;
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unsigned long reg_addr;
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u32 bit_mask, shift_bits;
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struct starfive_gpio_chip *chip =
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container_of(gp->chip, struct starfive_gpio_chip, chip);
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/* set out en*/
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reg_addr = chip->addr + gp->offset;
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reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
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shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
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<< STARFIVE_GPIO_SHIFT_BITS;
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bit_mask = STARFIVE_GPIO_MASK << shift_bits;
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val = readl((void *)reg_addr);
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val &= ~bit_mask;
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writel(val, (void *)reg_addr);
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return 0;
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}
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static void starfive_gpio_set(struct gpio_pin *gp, int value)
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{
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u32 val;
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unsigned long reg_addr;
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u32 bit_mask, shift_bits;
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struct starfive_gpio_chip *chip =
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container_of(gp->chip, struct starfive_gpio_chip, chip);
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reg_addr = chip->addr + gp->offset;
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reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
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shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
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<< STARFIVE_GPIO_SHIFT_BITS;
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bit_mask = STARFIVE_GPIO_MASK << shift_bits;
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/* set output value */
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val = readl((void *)(reg_addr + STARFIVE_GPIO_OUTVAL));
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val &= ~bit_mask;
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val |= value << shift_bits;
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writel(val, (void *)(reg_addr + STARFIVE_GPIO_OUTVAL));
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}
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extern struct fdt_gpio fdt_gpio_starfive;
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static int starfive_gpio_init(const void *fdt, int nodeoff,
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const struct fdt_match *match)
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{
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int rc;
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struct starfive_gpio_chip *chip;
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u64 addr;
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chip = sbi_zalloc(sizeof(*chip));
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if (!chip)
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return SBI_ENOMEM;
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rc = fdt_get_node_addr_size(fdt, nodeoff, 0, &addr, NULL);
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if (rc) {
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sbi_free(chip);
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return rc;
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}
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chip->addr = addr;
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chip->chip.driver = &fdt_gpio_starfive;
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chip->chip.id = nodeoff;
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chip->chip.ngpio = STARFIVE_GPIO_PINS_DEF;
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chip->chip.direction_output = starfive_gpio_direction_output;
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chip->chip.set = starfive_gpio_set;
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rc = gpio_chip_add(&chip->chip);
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if (rc) {
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sbi_free(chip);
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return rc;
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}
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return 0;
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}
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static const struct fdt_match starfive_gpio_match[] = {
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{ .compatible = "starfive,jh7110-sys-pinctrl" },
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{ .compatible = "starfive,iomux-pinctrl" },
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{ },
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};
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struct fdt_gpio fdt_gpio_starfive = {
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.match_table = starfive_gpio_match,
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.xlate = fdt_gpio_simple_xlate,
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.init = starfive_gpio_init,
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};
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