forked from Mirrors/opensbi
ce7c490719
Move Andes PLICSW ipi device to fdt ipi framework, this patch is based
on Leo's modified IPI scheme on PLICSW.
Current IPI scheme uses bit 0 of pending reigster on PLICSW to send IPI
from hart 0 to hart 7, but bit 0 needs to be hardwired to 0 according
to spec. After some investigation, self-IPI seems to be seldom or never
used, so we re-order the IPI scheme to support 8 core platforms.
dts example (Quad-core AX45MP):
plicsw: interrupt-controller@e6400000 {
compatible = "andestech,plicsw";
reg = <0x00000000 0xe6400000 0x00000000 0x00400000>;
interrupts-extended = <&CPU0_intc 3
&CPU1_intc 3
&CPU2_intc 3
&CPU3_intc 3>;
interrupt-controller;
#address-cells = <2>;
#interrupt-cells = <2>;
};
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
35 lines
627 B
Plaintext
35 lines
627 B
Plaintext
# SPDX-License-Identifier: BSD-2-Clause
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config PLATFORM_ANDES_AE350
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bool
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select FDT
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select FDT_SERIAL
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select FDT_SERIAL_UART8250
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select FDT_TIMER
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select FDT_TIMER_PLMT
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select FDT_RESET
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select FDT_RESET_ATCWDT200
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select FDT_IRQCHIP
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select FDT_IRQCHIP_PLIC
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select FDT_IPI
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select FDT_IPI_PLICSW
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default y
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if PLATFORM_ANDES_AE350
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config PLATFORM_ANDES_AE350_NAME
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string "Platform default name"
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default "Andes AE350"
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config PLATFORM_ANDES_AE350_MAJOR_VER
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int "Platform major version"
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range 0 65535
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default 0
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config PLATFORM_ANDES_AE350_MINOR_VER
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int "Platform minor version"
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range 0 65535
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default 1
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endif
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