forked from Mirrors/opensbi
b5ae8e8a65
We generally don't get misaligned load/store traps from Linux/U-Boot compiled using GCC 8.2 or higher but this is not true with older GCC toolchains. To tackle this we add misaligned load/store trap handling adopted from BBL sources but much more simpler. (Note: BBL sources can be found at https://github.com/riscv/riscv-pk.git) Signed-off-by: Anup Patel <anup.patel@wdc.com>
25 lines
555 B
Makefile
25 lines
555 B
Makefile
#
|
|
# Copyright (c) 2018 Western Digital Corporation or its affiliates.
|
|
#
|
|
# Authors:
|
|
# Anup Patel <anup.patel@wdc.com>
|
|
#
|
|
# SPDX-License-Identifier: BSD-2-Clause
|
|
#
|
|
|
|
lib-objs-y += riscv_asm.o
|
|
lib-objs-y += riscv_atomic.o
|
|
lib-objs-y += riscv_locks.o
|
|
|
|
lib-objs-y += sbi_console.o
|
|
lib-objs-y += sbi_ecall.o
|
|
lib-objs-y += sbi_emulate_csr.o
|
|
lib-objs-y += sbi_hart.o
|
|
lib-objs-y += sbi_illegal_insn.o
|
|
lib-objs-y += sbi_init.o
|
|
lib-objs-y += sbi_ipi.o
|
|
lib-objs-y += sbi_misaligned_ldst.o
|
|
lib-objs-y += sbi_system.o
|
|
lib-objs-y += sbi_timer.o
|
|
lib-objs-y += sbi_trap.o
|