forked from Mirrors/opensbi
764a17d852
RISC-V SBI v0.3 specification defines a set of firmware events that can provide additional information about the current firmware context. All of the firmware event monitoring are enabled now. The firmware events must be defined as raw perf event with MSB set as specified in the specification. Reviewed-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
249 lines
6.3 KiB
C
249 lines
6.3 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_fp.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_misaligned_ldst.h>
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#include <sbi/sbi_pmu.h>
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#include <sbi/sbi_trap.h>
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#include <sbi/sbi_unpriv.h>
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union reg_data {
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u8 data_bytes[8];
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ulong data_ulong;
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u64 data_u64;
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};
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int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
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struct sbi_trap_regs *regs)
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{
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ulong insn, insn_len;
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union reg_data val;
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struct sbi_trap_info uptrap;
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int i, fp = 0, shift = 0, len = 0;
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sbi_pmu_ctr_incr_fw(SBI_PMU_FW_MISALIGNED_LOAD);
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if (tinst & 0x1) {
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/*
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* Bit[0] == 1 implies trapped instruction value is
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* transformed instruction or custom instruction.
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*/
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insn = tinst | INSN_16BIT_MASK;
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insn_len = (tinst & 0x2) ? INSN_LEN(insn) : 2;
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} else {
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/*
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* Bit[0] == 0 implies trapped instruction value is
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* zero or special value.
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*/
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insn = sbi_get_insn(regs->mepc, &uptrap);
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if (uptrap.cause) {
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uptrap.epc = regs->mepc;
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return sbi_trap_redirect(regs, &uptrap);
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}
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insn_len = INSN_LEN(insn);
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}
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if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
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len = 4;
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shift = 8 * (sizeof(ulong) - len);
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#if __riscv_xlen == 64
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} else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) {
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len = 8;
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shift = 8 * (sizeof(ulong) - len);
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} else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) {
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len = 4;
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#endif
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#ifdef __riscv_flen
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} else if ((insn & INSN_MASK_FLD) == INSN_MATCH_FLD) {
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fp = 1;
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len = 8;
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} else if ((insn & INSN_MASK_FLW) == INSN_MATCH_FLW) {
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fp = 1;
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len = 4;
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#endif
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} else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) {
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len = 2;
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shift = 8 * (sizeof(ulong) - len);
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} else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) {
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len = 2;
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#if __riscv_xlen >= 64
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} else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) {
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len = 8;
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shift = 8 * (sizeof(ulong) - len);
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insn = RVC_RS2S(insn) << SH_RD;
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} else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP &&
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((insn >> SH_RD) & 0x1f)) {
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len = 8;
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shift = 8 * (sizeof(ulong) - len);
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#endif
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} else if ((insn & INSN_MASK_C_LW) == INSN_MATCH_C_LW) {
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len = 4;
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shift = 8 * (sizeof(ulong) - len);
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insn = RVC_RS2S(insn) << SH_RD;
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} else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP &&
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((insn >> SH_RD) & 0x1f)) {
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len = 4;
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shift = 8 * (sizeof(ulong) - len);
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#ifdef __riscv_flen
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} else if ((insn & INSN_MASK_C_FLD) == INSN_MATCH_C_FLD) {
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fp = 1;
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len = 8;
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insn = RVC_RS2S(insn) << SH_RD;
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} else if ((insn & INSN_MASK_C_FLDSP) == INSN_MATCH_C_FLDSP) {
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fp = 1;
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len = 8;
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#if __riscv_xlen == 32
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} else if ((insn & INSN_MASK_C_FLW) == INSN_MATCH_C_FLW) {
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fp = 1;
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len = 4;
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insn = RVC_RS2S(insn) << SH_RD;
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} else if ((insn & INSN_MASK_C_FLWSP) == INSN_MATCH_C_FLWSP) {
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fp = 1;
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len = 4;
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#endif
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#endif
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} else {
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uptrap.epc = regs->mepc;
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uptrap.cause = CAUSE_MISALIGNED_LOAD;
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uptrap.tval = addr;
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uptrap.tval2 = tval2;
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uptrap.tinst = tinst;
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return sbi_trap_redirect(regs, &uptrap);
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}
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val.data_u64 = 0;
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for (i = 0; i < len; i++) {
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val.data_bytes[i] = sbi_load_u8((void *)(addr + i),
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&uptrap);
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if (uptrap.cause) {
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uptrap.epc = regs->mepc;
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return sbi_trap_redirect(regs, &uptrap);
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}
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}
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if (!fp)
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SET_RD(insn, regs, ((long)(val.data_ulong << shift)) >> shift);
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#ifdef __riscv_flen
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else if (len == 8)
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SET_F64_RD(insn, regs, val.data_u64);
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else
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SET_F32_RD(insn, regs, val.data_ulong);
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#endif
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regs->mepc += insn_len;
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return 0;
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}
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int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
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struct sbi_trap_regs *regs)
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{
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ulong insn, insn_len;
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union reg_data val;
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struct sbi_trap_info uptrap;
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int i, len = 0;
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sbi_pmu_ctr_incr_fw(SBI_PMU_FW_MISALIGNED_STORE);
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if (tinst & 0x1) {
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/*
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* Bit[0] == 1 implies trapped instruction value is
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* transformed instruction or custom instruction.
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*/
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insn = tinst | INSN_16BIT_MASK;
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insn_len = (tinst & 0x2) ? INSN_LEN(insn) : 2;
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} else {
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/*
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* Bit[0] == 0 implies trapped instruction value is
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* zero or special value.
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*/
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insn = sbi_get_insn(regs->mepc, &uptrap);
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if (uptrap.cause) {
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uptrap.epc = regs->mepc;
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return sbi_trap_redirect(regs, &uptrap);
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}
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insn_len = INSN_LEN(insn);
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}
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val.data_ulong = GET_RS2(insn, regs);
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if ((insn & INSN_MASK_SW) == INSN_MATCH_SW) {
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len = 4;
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#if __riscv_xlen == 64
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} else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) {
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len = 8;
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#endif
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#ifdef __riscv_flen
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} else if ((insn & INSN_MASK_FSD) == INSN_MATCH_FSD) {
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len = 8;
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val.data_u64 = GET_F64_RS2(insn, regs);
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} else if ((insn & INSN_MASK_FSW) == INSN_MATCH_FSW) {
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len = 4;
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val.data_ulong = GET_F32_RS2(insn, regs);
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#endif
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} else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) {
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len = 2;
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#if __riscv_xlen >= 64
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} else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {
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len = 8;
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val.data_ulong = GET_RS2S(insn, regs);
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} else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP &&
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((insn >> SH_RD) & 0x1f)) {
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len = 8;
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val.data_ulong = GET_RS2C(insn, regs);
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#endif
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} else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) {
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len = 4;
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val.data_ulong = GET_RS2S(insn, regs);
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} else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP &&
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((insn >> SH_RD) & 0x1f)) {
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len = 4;
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val.data_ulong = GET_RS2C(insn, regs);
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#ifdef __riscv_flen
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} else if ((insn & INSN_MASK_C_FSD) == INSN_MATCH_C_FSD) {
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len = 8;
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val.data_u64 = GET_F64_RS2S(insn, regs);
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} else if ((insn & INSN_MASK_C_FSDSP) == INSN_MATCH_C_FSDSP) {
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len = 8;
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val.data_u64 = GET_F64_RS2C(insn, regs);
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#if __riscv_xlen == 32
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} else if ((insn & INSN_MASK_C_FSW) == INSN_MATCH_C_FSW) {
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len = 4;
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val.data_ulong = GET_F32_RS2S(insn, regs);
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} else if ((insn & INSN_MASK_C_FSWSP) == INSN_MATCH_C_FSWSP) {
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len = 4;
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val.data_ulong = GET_F32_RS2C(insn, regs);
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#endif
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#endif
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} else {
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uptrap.epc = regs->mepc;
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uptrap.cause = CAUSE_MISALIGNED_STORE;
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uptrap.tval = addr;
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uptrap.tval2 = tval2;
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uptrap.tinst = tinst;
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return sbi_trap_redirect(regs, &uptrap);
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}
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for (i = 0; i < len; i++) {
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sbi_store_u8((void *)(addr + i), val.data_bytes[i],
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&uptrap);
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if (uptrap.cause) {
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uptrap.epc = regs->mepc;
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return sbi_trap_redirect(regs, &uptrap);
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}
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}
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regs->mepc += insn_len;
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return 0;
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}
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