forked from Mirrors/opensbi
764a17d852
RISC-V SBI v0.3 specification defines a set of firmware events that can provide additional information about the current firmware context. All of the firmware event monitoring are enabled now. The firmware events must be defined as raw perf event with MSB set as specified in the specification. Reviewed-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
146 lines
3.6 KiB
C
146 lines
3.6 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_emulate_csr.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_illegal_insn.h>
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#include <sbi/sbi_pmu.h>
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#include <sbi/sbi_trap.h>
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#include <sbi/sbi_unpriv.h>
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typedef int (*illegal_insn_func)(ulong insn, struct sbi_trap_regs *regs);
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static int truly_illegal_insn(ulong insn, struct sbi_trap_regs *regs)
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{
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struct sbi_trap_info trap;
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trap.epc = regs->mepc;
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trap.cause = CAUSE_ILLEGAL_INSTRUCTION;
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trap.tval = insn;
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trap.tval2 = 0;
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trap.tinst = 0;
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return sbi_trap_redirect(regs, &trap);
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}
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static int system_opcode_insn(ulong insn, struct sbi_trap_regs *regs)
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{
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int do_write, rs1_num = (insn >> 15) & 0x1f;
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ulong rs1_val = GET_RS1(insn, regs);
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int csr_num = (u32)insn >> 20;
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ulong csr_val, new_csr_val;
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/* TODO: Ensure that we got CSR read/write instruction */
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if (sbi_emulate_csr_read(csr_num, regs, &csr_val))
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return truly_illegal_insn(insn, regs);
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do_write = rs1_num;
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switch (GET_RM(insn)) {
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case 1:
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new_csr_val = rs1_val;
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do_write = 1;
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break;
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case 2:
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new_csr_val = csr_val | rs1_val;
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break;
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case 3:
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new_csr_val = csr_val & ~rs1_val;
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break;
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case 5:
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new_csr_val = rs1_num;
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do_write = 1;
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break;
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case 6:
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new_csr_val = csr_val | rs1_num;
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break;
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case 7:
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new_csr_val = csr_val & ~rs1_num;
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break;
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default:
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return truly_illegal_insn(insn, regs);
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};
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if (do_write && sbi_emulate_csr_write(csr_num, regs, new_csr_val))
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return truly_illegal_insn(insn, regs);
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SET_RD(insn, regs, csr_val);
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regs->mepc += 4;
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return 0;
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}
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static illegal_insn_func illegal_insn_table[32] = {
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truly_illegal_insn, /* 0 */
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truly_illegal_insn, /* 1 */
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truly_illegal_insn, /* 2 */
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truly_illegal_insn, /* 3 */
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truly_illegal_insn, /* 4 */
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truly_illegal_insn, /* 5 */
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truly_illegal_insn, /* 6 */
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truly_illegal_insn, /* 7 */
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truly_illegal_insn, /* 8 */
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truly_illegal_insn, /* 9 */
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truly_illegal_insn, /* 10 */
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truly_illegal_insn, /* 11 */
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truly_illegal_insn, /* 12 */
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truly_illegal_insn, /* 13 */
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truly_illegal_insn, /* 14 */
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truly_illegal_insn, /* 15 */
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truly_illegal_insn, /* 16 */
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truly_illegal_insn, /* 17 */
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truly_illegal_insn, /* 18 */
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truly_illegal_insn, /* 19 */
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truly_illegal_insn, /* 20 */
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truly_illegal_insn, /* 21 */
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truly_illegal_insn, /* 22 */
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truly_illegal_insn, /* 23 */
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truly_illegal_insn, /* 24 */
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truly_illegal_insn, /* 25 */
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truly_illegal_insn, /* 26 */
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truly_illegal_insn, /* 27 */
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system_opcode_insn, /* 28 */
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truly_illegal_insn, /* 29 */
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truly_illegal_insn, /* 30 */
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truly_illegal_insn /* 31 */
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};
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int sbi_illegal_insn_handler(ulong insn, struct sbi_trap_regs *regs)
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{
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struct sbi_trap_info uptrap;
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/*
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* We only deal with 32-bit (or longer) illegal instructions. If we
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* see instruction is zero OR instruction is 16-bit then we fetch and
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* check the instruction encoding using unprivilege access.
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*
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* The program counter (PC) in RISC-V world is always 2-byte aligned
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* so handling only 32-bit (or longer) illegal instructions also help
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* the case where MTVAL CSR contains instruction address for illegal
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* instruction trap.
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*/
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sbi_pmu_ctr_incr_fw(SBI_PMU_FW_ILLEGAL_INSN);
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if (unlikely((insn & 3) != 3)) {
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insn = sbi_get_insn(regs->mepc, &uptrap);
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if (uptrap.cause) {
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uptrap.epc = regs->mepc;
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return sbi_trap_redirect(regs, &uptrap);
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}
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if ((insn & 3) != 3)
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return truly_illegal_insn(insn, regs);
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}
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return illegal_insn_table[(insn & 0x7c) >> 2](insn, regs);
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}
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