forked from Mirrors/opensbi
32f87e5a86
This patch contains the following AE350 specific SBIs: - get mcache_ctl status - get mmisc_ctl status - set mcache_ctl status - set mmisc_ctl status - I-cache operation - D-cache operation - enable/disable L1-I-cache prefetch - enable/disable L1-D-cache prefetch - enable/disable non-blocking load store - enable/disable write-around Signed-off-by: Nylon Chen <nylon7@andestech.com> Reviewed-by: Anup Patel <Anup.Patel@wdc.com> Reviewed-by: Atish Patra <Atish.Patra@wdc.com>
126 lines
4.6 KiB
C
126 lines
4.6 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Andes Technology Corporation
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*
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* Authors:
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* Zong Li <zong@andestech.com>
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* Nylon Chen <nylon7@andestech.com>
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*/
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#ifndef _AE350_PLATFORM_H_
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#define _AE350_PLATFORM_H_
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#define AE350_HART_COUNT 4
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#define AE350_PLIC_ADDR 0xe4000000
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#define AE350_PLIC_NUM_SOURCES 71
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#define AE350_PLICSW_ADDR 0xe6400000
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#define AE350_PLMT_ADDR 0xe6000000
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#define AE350_L2C_ADDR 0xe0500000
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#define AE350_UART_ADDR_OFFSET 0x20
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#define AE350_UART_ADDR (0xf0300000 + AE350_UART_ADDR_OFFSET)
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#define AE350_UART_FREQUENCY 19660800
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#define AE350_UART_BAUDRATE 38400
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#define AE350_UART_REG_SHIFT 2
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#define AE350_UART_REG_WIDTH 0
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/*Memory and Miscellaneous Registers*/
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#define CSR_MILMB 0x7c0
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#define CSR_MDLMB 0x7c1
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#define CSR_MECC_CDOE 0x7c2
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#define CSR_MNVEC 0x7c3
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#define CSR_MPFTCTL 0x7c5
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#define CSR_MCACHECTL 0x7ca
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#define CSR_MCCTLBEGINADDR 0x7cb
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#define CSR_MCCTLCOMMAND 0x7cc
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#define CSR_MCCTLDATA 0x7cc
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#define CSR_SCCTLDATA 0x9cd
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#define CSR_UCCTLBEGINADDR 0x80c
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#define CSR_MMISCCTL 0x7d0
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enum sbi_ext_andes_fid {
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SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS = 0,
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SBI_EXT_ANDES_GET_MMISC_CTL_STATUS,
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SBI_EXT_ANDES_SET_MCACHE_CTL,
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SBI_EXT_ANDES_SET_MMISC_CTL,
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SBI_EXT_ANDES_ICACHE_OP,
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SBI_EXT_ANDES_DCACHE_OP,
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SBI_EXT_ANDES_L1CACHE_I_PREFETCH,
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SBI_EXT_ANDES_L1CACHE_D_PREFETCH,
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SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE,
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SBI_EXT_ANDES_WRITE_AROUND,
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};
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/* nds v5 mmisc_ctl register*/
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#define V5_MMISC_CTL_VEC_PLIC_OFFSET 1
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#define V5_MMISC_CTL_RVCOMPM_OFFSET 2
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#define V5_MMISC_CTL_BRPE_OFFSET 3
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#define V5_MMISC_CTL_MSA_OR_UNA_OFFSET 6
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#define V5_MMISC_CTL_NON_BLOCKING_OFFSET 8
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#define V5_MCACHE_CTL_L1I_PREFETCH_OFFSET 9
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#define V5_MCACHE_CTL_L1D_PREFETCH_OFFSET 10
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#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_1 13
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#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_2 14
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#define V5_MMISC_CTL_VEC_PLIC_EN (1UL << V5_MMISC_CTL_VEC_PLIC_OFFSET)
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#define V5_MMISC_CTL_RVCOMPM_EN (1UL << V5_MMISC_CTL_RVCOMPM_OFFSET)
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#define V5_MMISC_CTL_BRPE_EN (1UL << V5_MMISC_CTL_BRPE_OFFSET)
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#define V5_MMISC_CTL_MSA_OR_UNA_EN (1UL << V5_MMISC_CTL_MSA_OR_UNA_OFFSET)
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#define V5_MMISC_CTL_NON_BLOCKING_EN (1UL << V5_MMISC_CTL_NON_BLOCKING_OFFSET)
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#define V5_MCACHE_CTL_L1I_PREFETCH_EN (1UL << V5_MCACHE_CTL_L1I_PREFETCH_OFFSET)
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#define V5_MCACHE_CTL_L1D_PREFETCH_EN (1UL << V5_MCACHE_CTL_L1D_PREFETCH_OFFSET)
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#define V5_MCACHE_CTL_DC_WAROUND_1_EN (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_1)
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#define V5_MCACHE_CTL_DC_WAROUND_2_EN (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_2)
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#define V5_MMISC_CTL_MASK (V5_MMISC_CTL_VEC_PLIC_EN | V5_MMISC_CTL_RVCOMPM_EN \
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| V5_MMISC_CTL_BRPE_EN | V5_MMISC_CTL_MSA_OR_UNA_EN | V5_MMISC_CTL_NON_BLOCKING_EN)
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/* nds mcache_ctl register*/
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#define V5_MCACHE_CTL_IC_EN_OFFSET 0
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#define V5_MCACHE_CTL_DC_EN_OFFSET 1
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#define V5_MCACHE_CTL_IC_ECCEN_OFFSET 2
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#define V5_MCACHE_CTL_DC_ECCEN_OFFSET 4
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#define V5_MCACHE_CTL_IC_RWECC_OFFSET 6
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#define V5_MCACHE_CTL_DC_RWECC_OFFSET 7
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#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8
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/*nds cctl command*/
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#define V5_UCCTL_L1D_WBINVAL_ALL 6
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#define V5_UCCTL_L1D_WB_ALL 7
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#define V5_MCACHE_CTL_IC_EN (1UL << V5_MCACHE_CTL_IC_EN_OFFSET)
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#define V5_MCACHE_CTL_DC_EN (1UL << V5_MCACHE_CTL_DC_EN_OFFSET)
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#define V5_MCACHE_CTL_IC_RWECC (1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET)
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#define V5_MCACHE_CTL_DC_RWECC (1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET)
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#define V5_MCACHE_CTL_CCTL_SUEN (1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
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#define V5_MCACHE_CTL_MASK (V5_MCACHE_CTL_IC_EN | V5_MCACHE_CTL_DC_EN \
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| V5_MCACHE_CTL_IC_RWECC | V5_MCACHE_CTL_DC_RWECC \
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| V5_MCACHE_CTL_CCTL_SUEN | V5_MCACHE_CTL_L1I_PREFETCH_EN \
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| V5_MCACHE_CTL_L1D_PREFETCH_EN | V5_MCACHE_CTL_DC_WAROUND_1_EN \
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| V5_MCACHE_CTL_DC_WAROUND_2_EN)
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#define V5_L2C_CTL_OFFSET 0x8
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#define V5_L2C_CTL_ENABLE_OFFSET 0
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#define V5_L2C_CTL_IPFDPT_OFFSET 3
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#define V5_L2C_CTL_DPFDPT_OFFSET 5
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#define V5_L2C_CTL_TRAMOCTL_OFFSET 8
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#define V5_L2C_CTL_TRAMICTL_OFFSET 10
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#define V5_L2C_CTL_DRAMOCTL_OFFSET 11
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#define V5_L2C_CTL_DRAMICTL_OFFSET 13
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#define V5_L2C_CTL_ENABLE_MASK (1UL << V5_L2C_CTL_ENABLE_OFFSET)
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#define V5_L2C_CTL_IPFDPT_MASK (3UL << V5_L2C_CTL_IPFDPT_OFFSET)
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#define V5_L2C_CTL_DPFDPT_MASK (3UL << V5_L2C_CTL_DPFDPT_OFFSET)
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#define V5_L2C_CTL_TRAMOCTL_MASK (3UL << V5_L2C_CTL_TRAMOCTL_OFFSET)
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#define V5_L2C_CTL_TRAMICTL_MASK (1UL << V5_L2C_CTL_TRAMICTL_OFFSET)
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#define V5_L2C_CTL_DRAMOCTL_MASK (3UL << V5_L2C_CTL_DRAMOCTL_OFFSET)
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#define V5_L2C_CTL_DRAMICTL_MASK (1UL << V5_L2C_CTL_DRAMICTL_OFFSET)
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#endif /* _AE350_PLATFORM_H_ */
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