forked from Mirrors/opensbi
2dd6eaf680
Currently, each platform keeps track of which irqchip driver is in use and calls its warm init function. Since the generic platform may use multiple irqchip drivers, it has logic to track an array of drivers. The code is simplified and made common across platforms by treating warm init and exit as properties of the driver, not the platform. Then the platform's only role is to select and prepare a driver during cold boot. For now, only add a .warm_init hook, since none of the existing drivers need an .exit hook. It could be added in the future if needed. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
153 lines
3.6 KiB
C
153 lines
3.6 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2019 FORTH-ICS/CARV
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* Panagiotis Peristerakis <perister@ics.forth.gr>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/fdt/fdt_fixup.h>
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#include <sbi_utils/ipi/aclint_mswi.h>
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#include <sbi_utils/irqchip/plic.h>
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#include <sbi_utils/serial/uart8250.h>
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#include <sbi_utils/timer/aclint_mtimer.h>
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#define ARIANE_UART_ADDR 0x10000000
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#define ARIANE_UART_FREQ 50000000
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#define ARIANE_UART_BAUDRATE 115200
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#define ARIANE_UART_REG_SHIFT 2
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#define ARIANE_UART_REG_WIDTH 4
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#define ARIANE_UART_REG_OFFSET 0
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#define ARIANE_PLIC_ADDR 0xc000000
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#define ARIANE_PLIC_SIZE (0x200000 + \
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(ARIANE_HART_COUNT * 0x1000))
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#define ARIANE_PLIC_NUM_SOURCES 3
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#define ARIANE_HART_COUNT 1
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#define ARIANE_CLINT_ADDR 0x2000000
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#define ARIANE_ACLINT_MTIMER_FREQ 1000000
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#define ARIANE_ACLINT_MSWI_ADDR (ARIANE_CLINT_ADDR + \
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CLINT_MSWI_OFFSET)
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#define ARIANE_ACLINT_MTIMER_ADDR (ARIANE_CLINT_ADDR + \
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CLINT_MTIMER_OFFSET)
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static struct plic_data plic = {
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.addr = ARIANE_PLIC_ADDR,
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.size = ARIANE_PLIC_SIZE,
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.num_src = ARIANE_PLIC_NUM_SOURCES,
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.flags = PLIC_FLAG_ARIANE_BUG,
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.context_map = {
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[0] = { 0, 1 },
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},
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};
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static struct aclint_mswi_data mswi = {
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.addr = ARIANE_ACLINT_MSWI_ADDR,
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.size = ACLINT_MSWI_SIZE,
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.first_hartid = 0,
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.hart_count = ARIANE_HART_COUNT,
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};
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static struct aclint_mtimer_data mtimer = {
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.mtime_freq = ARIANE_ACLINT_MTIMER_FREQ,
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.mtime_addr = ARIANE_ACLINT_MTIMER_ADDR +
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ACLINT_DEFAULT_MTIME_OFFSET,
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.mtime_size = ACLINT_DEFAULT_MTIME_SIZE,
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.mtimecmp_addr = ARIANE_ACLINT_MTIMER_ADDR +
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ACLINT_DEFAULT_MTIMECMP_OFFSET,
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.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
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.first_hartid = 0,
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.hart_count = ARIANE_HART_COUNT,
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.has_64bit_mmio = true,
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};
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/*
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* Ariane platform early initialization.
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*/
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static int ariane_early_init(bool cold_boot)
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{
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if (!cold_boot)
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return 0;
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return uart8250_init(ARIANE_UART_ADDR,
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ARIANE_UART_FREQ,
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ARIANE_UART_BAUDRATE,
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ARIANE_UART_REG_SHIFT,
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ARIANE_UART_REG_WIDTH,
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ARIANE_UART_REG_OFFSET);
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}
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/*
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* Ariane platform final initialization.
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*/
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static int ariane_final_init(bool cold_boot)
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{
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void *fdt;
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if (!cold_boot)
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return 0;
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fdt = fdt_get_address_rw();
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fdt_fixups(fdt);
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return 0;
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}
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/*
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* Initialize the ariane interrupt controller for current HART.
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*/
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static int ariane_irqchip_init(bool cold_boot)
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{
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int ret;
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if (cold_boot) {
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ret = plic_cold_irqchip_init(&plic);
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if (ret)
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return ret;
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}
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return 0;
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}
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/*
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* Initialize IPI during cold boot.
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*/
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static int ariane_ipi_init(void)
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{
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return aclint_mswi_cold_init(&mswi);
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}
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/*
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* Initialize ariane timer during cold boot.
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*/
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static int ariane_timer_init(void)
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{
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return aclint_mtimer_cold_init(&mtimer, NULL);
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}
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/*
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* Platform descriptor.
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*/
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const struct sbi_platform_operations platform_ops = {
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.early_init = ariane_early_init,
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.final_init = ariane_final_init,
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.irqchip_init = ariane_irqchip_init,
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.ipi_init = ariane_ipi_init,
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.timer_init = ariane_timer_init,
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};
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const struct sbi_platform platform = {
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.opensbi_version = OPENSBI_VERSION,
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.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
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.name = "ARIANE RISC-V",
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.features = SBI_PLATFORM_DEFAULT_FEATURES,
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.hart_count = ARIANE_HART_COUNT,
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.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
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.heap_size = SBI_PLATFORM_DEFAULT_HEAP_SIZE(ARIANE_HART_COUNT),
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.platform_ops_addr = (unsigned long)&platform_ops
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};
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