forked from Mirrors/opensbi
1bb00ab3ae
The default (usually last) PMP region provides S-mode access to complete memory range not covered by other PMP regions. Currently, the default PMP region is described as platform specific PMP region which is not appropriate because all platforms need it and default PMP region should be part of generic library. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
161 lines
3.7 KiB
C
161 lines
3.7 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Andes Technology Corporation
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*
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* Authors:
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* Zong Li <zong@andestech.com>
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* Nylon Chen <nylon7@andestech.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_platform.h>
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#include <sbi_utils/fdt/fdt_fixup.h>
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#include <sbi_utils/irqchip/plic.h>
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#include <sbi_utils/serial/uart8250.h>
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#include "platform.h"
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#include "plicsw.h"
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#include "plmt.h"
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/* Platform final initialization. */
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static int ae350_final_init(bool cold_boot)
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{
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void *fdt;
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/* enable L1 cache */
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uintptr_t mcache_ctl_val = csr_read(CSR_MCACHECTL);
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if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
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mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
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if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
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mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
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if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN))
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mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN;
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csr_write(CSR_MCACHECTL, mcache_ctl_val);
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/* enable L2 cache */
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uint32_t *l2c_ctl_base = (void *)AE350_L2C_ADDR + V5_L2C_CTL_OFFSET;
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uint32_t l2c_ctl_val = *l2c_ctl_base;
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if (!(l2c_ctl_val & V5_L2C_CTL_ENABLE_MASK))
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l2c_ctl_val |= V5_L2C_CTL_ENABLE_MASK;
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*l2c_ctl_base = l2c_ctl_val;
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if (!cold_boot)
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return 0;
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fdt = sbi_scratch_thishart_arg1_ptr();
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fdt_fixups(fdt);
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return 0;
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}
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/* Initialize the platform console. */
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static int ae350_console_init(void)
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{
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return uart8250_init(AE350_UART_ADDR,
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AE350_UART_FREQUENCY,
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AE350_UART_BAUDRATE,
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AE350_UART_REG_SHIFT,
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AE350_UART_REG_WIDTH);
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}
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/* Initialize the platform interrupt controller for current HART. */
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static int ae350_irqchip_init(bool cold_boot)
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{
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u32 hartid = current_hartid();
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int ret;
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if (cold_boot) {
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ret = plic_cold_irqchip_init(AE350_PLIC_ADDR,
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AE350_PLIC_NUM_SOURCES,
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AE350_HART_COUNT);
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if (ret)
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return ret;
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}
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return plic_warm_irqchip_init(hartid, 2 * hartid, 2 * hartid + 1);
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}
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/* Initialize IPI for current HART. */
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static int ae350_ipi_init(bool cold_boot)
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{
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int ret;
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if (cold_boot) {
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ret = plicsw_cold_ipi_init(AE350_PLICSW_ADDR,
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AE350_HART_COUNT);
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if (ret)
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return ret;
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}
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return plicsw_warm_ipi_init();
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}
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/* Initialize platform timer for current HART. */
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static int ae350_timer_init(bool cold_boot)
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{
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int ret;
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if (cold_boot) {
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ret = plmt_cold_timer_init(AE350_PLMT_ADDR,
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AE350_HART_COUNT);
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if (ret)
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return ret;
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}
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return plmt_warm_timer_init();
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}
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/* Reboot the platform. */
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static int ae350_system_reboot(u32 type)
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{
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/* For now nothing to do. */
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sbi_printf("System reboot\n");
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return 0;
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}
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/* Shutdown or poweroff the platform. */
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static int ae350_system_shutdown(u32 type)
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{
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/* For now nothing to do. */
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sbi_printf("System shutdown\n");
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return 0;
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}
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/* Platform descriptor. */
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const struct sbi_platform_operations platform_ops = {
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.final_init = ae350_final_init,
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.console_init = ae350_console_init,
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.console_putc = uart8250_putc,
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.console_getc = uart8250_getc,
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.irqchip_init = ae350_irqchip_init,
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.ipi_init = ae350_ipi_init,
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.ipi_send = plicsw_ipi_send,
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.ipi_clear = plicsw_ipi_clear,
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.timer_init = ae350_timer_init,
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.timer_value = plmt_timer_value,
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.timer_event_start = plmt_timer_event_start,
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.timer_event_stop = plmt_timer_event_stop,
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.system_reboot = ae350_system_reboot,
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.system_shutdown = ae350_system_shutdown
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};
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const struct sbi_platform platform = {
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.opensbi_version = OPENSBI_VERSION,
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.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
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.name = "Andes AE350",
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.features = SBI_PLATFORM_DEFAULT_FEATURES,
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.hart_count = AE350_HART_COUNT,
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.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
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.platform_ops_addr = (unsigned long)&platform_ops
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};
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