forked from Mirrors/opensbi
0c304b6619
A platform may use programmable counters for cycle/instret events. The priv spec allows that provided that cycle/instret also report those events in addition to the programmable counters. We should allow that functionality in OpenSBI. Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
75 lines
2.3 KiB
C
75 lines
2.3 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Atish Patra <atish.patra@wdc.com>
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*/
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#ifndef __SBI_PMU_H__
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#define __SBI_PMU_H__
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#include <sbi/sbi_types.h>
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#include <sbi/sbi_hartmask.h>
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#include <sbi/sbi_scratch.h>
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#include <sbi/sbi_ecall_interface.h>
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/* Event related macros */
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/* Maximum number of hardware events that can mapped by OpenSBI */
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#define SBI_PMU_HW_EVENT_MAX 64
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/* Maximum number of firmware events that can mapped by OpenSBI */
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#define SBI_PMU_FW_EVENT_MAX 32
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/* Counter related macros */
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#define SBI_PMU_FW_CTR_MAX 16
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#define SBI_PMU_HW_CTR_MAX 32
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#define SBI_PMU_CTR_MAX (SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX)
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#define SBI_PMU_FIXED_CTR_MASK 0x07
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/** Initialize PMU */
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int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot);
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/** Reset PMU during hart exit */
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void sbi_pmu_exit(struct sbi_scratch *scratch);
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/**
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* Add the hardware event to counter mapping information. This should be called
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* from the platform code to update the mapping table.
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* @param eidx_start Start of the event idx range for supported counters
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* @param eidx_end End of the event idx range for supported counters
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* @param cmap A bitmap representing counters supporting the event range
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* @return 0 on success, error otherwise.
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*/
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int sbi_pmu_add_hw_event_counter_map(u32 eidx_start, u32 eidx_end, u32 cmap);
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/**
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* Add the raw hardware event selector and supported counter information. This
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* should be called from the platform code to update the mapping table.
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* @param info a pointer to the hardware event info
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* @return 0 on success, error otherwise.
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*/
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int sbi_pmu_add_raw_event_counter_map(uint64_t select, u32 cmap);
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int sbi_pmu_ctr_read(uint32_t cidx, unsigned long *cval);
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int sbi_pmu_ctr_stop(unsigned long cidx_base, unsigned long cidx_mask,
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unsigned long flag);
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int sbi_pmu_ctr_start(unsigned long cidx_base, unsigned long cidx_mask,
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unsigned long flags, uint64_t ival);
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int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info);
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unsigned long sbi_pmu_num_ctr(void);
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int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask,
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unsigned long flags, unsigned long event_idx,
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uint64_t event_data);
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int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id);
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#endif
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