forked from Mirrors/opensbi
49e422c5ad
This driver is for T-HEAD test chip, fpga. It could work with
all T-HEAD riscv processors: C9xx series.
example1: (Using io-regs for reset)
reset: reset-sample {
compatible = "thead,reset-sample";
plic-delegate = <0xff 0xd81ffffc>;
entry-reg = <0xff 0xff019050>;
entry-cnt = <4>;
control-reg = <0xff 0xff015004>;
control-val = <0x1c>;
csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
};
example2: (Using csr-regs for reset)
reset: reset-sample {
compatible = "thead,reset-sample";
plic-delegate = <0xff 0xd81ffffc>;
using-csr-reset;
csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
0x3b0 0x3b1 0x3b2 0x3b3
0x3b4 0x3b5 0x3b6 0x3b7
0x3a0>;
};
example3: (Only delegate plic enable to S-mode)
reset: reset-sample {
compatible = "thead,reset-sample";
plic-delegate = <0xff 0xd81ffffc>;
};
After this patch, all T-HEAD c9xx would use platform/generic with fw_dynamic
as default:
CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y /usr/bin/make
The platform/thead will be deprecated.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
61 lines
1.3 KiB
C
61 lines
1.3 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#ifndef __RISCV_BARRIER_H__
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#define __RISCV_BARRIER_H__
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/* clang-format off */
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#define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n"
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#define RISCV_RELEASE_BARRIER "\tfence rw, w\n"
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#define RISCV_FENCE(p, s) \
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__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
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#define RISCV_FENCE_I \
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__asm__ __volatile__ ("fence.i" : : : "memory")
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/* Read & Write Memory barrier */
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#define mb() RISCV_FENCE(iorw,iorw)
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/* Read Memory barrier */
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#define rmb() RISCV_FENCE(ir,ir)
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/* Write Memory barrier */
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#define wmb() RISCV_FENCE(ow,ow)
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/* SMP Read & Write Memory barrier */
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#define smp_mb() RISCV_FENCE(rw,rw)
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/* SMP Read Memory barrier */
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#define smp_rmb() RISCV_FENCE(r,r)
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/* SMP Write Memory barrier */
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#define smp_wmb() RISCV_FENCE(w,w)
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/* CPU relax for busy loop */
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#define cpu_relax() asm volatile ("" : : : "memory")
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/* clang-format on */
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#define __smp_store_release(p, v) \
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do { \
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RISCV_FENCE(rw, w); \
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*(p) = (v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = *(p); \
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RISCV_FENCE(r, rw); \
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___p1; \
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})
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#endif
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