Samuel Holland 9dc5ec5c51 platform: Add HSM implementation for Allwinner D1 ...

Allwinner D1 contains a "PPU" power domain controller which can
automatically power down/up the CPU power domain. This power domain
includes the C906 core along with its CLINT and PLIC.

This HSM implementation supports non-retentive hart suspend by:
  1) Saving/restoring state that is lost during hart suspend,
  2) Performing cache maintenance before/after hart suspend,
  3) Configuring wakeup sources before hart suspend, and
  4) Asking the PPU to power down the hart when it enters WFI.

Since this HSM implementation is for a single-core SoC, it does not need
to worry about concurrency or saving multiple instances of state.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>

2022-06-13 11:59:09 +05:30

..

andes/ae350

lib: utils/serial: support 'reg-offset' property

2022-04-17 13:57:48 +05:30

fpga

lib: irqchip/plic: Factor out a context init function

2022-06-13 11:54:06 +05:30

generic

platform: Add HSM implementation for Allwinner D1

2022-06-13 11:59:09 +05:30

kendryte/k210

include: sbi_utils: Introduce an helper to get fdt base address

2021-11-02 11:23:16 +05:30

nuclei/ux600

include: sbi_utils: Introduce an helper to get fdt base address

2021-11-02 11:23:16 +05:30

template

lib: utils/serial: support 'reg-offset' property

2022-04-17 13:57:48 +05:30