Commit Graph

16 Commits

Author SHA1 Message Date
Atish Patra
ae72ec0915 utils: fdt: Add fdt helper functions to parse PMU DT nodes
The PMU DT node bindings are defined in docs/pmu_support.md
Add few fdt helper functions to parse the DT node and update the
event-counter mapping tables.

Reviewed-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
2021-07-11 10:27:57 +05:30
Bin Meng
4edc822407 lib/utils: Support fixing up the official DT bindings of PLIC
Current fdt_plic_fixup() only does necessary fix-up against the legacy
"riscv,plic0" node. The upstream Linux kernel defines its official DT
bindings which uses "sifive,plic-1.0.0" as the compatible string and
we should check that first, and if not present fall back to legacy.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2021-04-01 10:31:11 +05:30
Bin Meng
ca3f35821b lib/utils: Drop the 'compat' parameter of fdt_plic_fixup()
At present fdt_plic_fixup() accepts a 'compat' parameter for PLIC
compatible string. In preparation to support the new DT bindings,
drop this and use "riscv,plic0" directly in fdt_plic_fixup().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2021-04-01 10:27:28 +05:30
Anup Patel
5fd99dbdaa lib: utils: Update fdt_cpu_fixup() to use current domain
The fdt_cpu_fixup() should disable a HART in DT if the HART
is not assigned to the current HART domain. This patch updates
fdt_cpu_fixup() accordingly.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-10-20 14:04:51 +05:30
Anup Patel
5edbb7cda1 lib: utils: Update fdt_reserved_memory_fixup() to use current domain
Now that each HART is mapped to a domain having a set of memory
regions, we update fdt_reserved_memory_fixup() to use domain memory
regions for adding reserved memory nodes in device tree.

We also change reserved memory node name prefix from "mmode_pmp"
to "mmode_resv" because domain memory regions can impact other
hardware configurations (such as IOPMP, etc) along with PMP.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-10-20 14:04:43 +05:30
Anup Patel
9f935a4a43 lib: utils: Improve fdt_cpu_fixup() implementation
The fdt_cpu_fixup() should work fine even if HARTs without MMU
are not marked invalid by platform support code.

In future, we plan to treat HARTs without MMU as valid in the
generic platform support so that we can hold these HARTs in
HSM STOPPED state.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-16 09:05:27 +05:30
Anup Patel
7b0b289887 lib: sbi: Remove redundant SBI_HART_HAS_PMP feature
The SBI_HART_HAS_PMP feature is redundant because we already
have number of PMP regions returned by sbi_hart_pmp_count().

Checking whether PMP is supported for a HART can be simply done
by checking non-zero value returned by sbi_hart_pmp_count().

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-01 10:28:26 +05:30
Bin Meng
a5f9104330 lib/utils: fdt: Update FDT expand size to 1024 for reserved memory node
Currently 256 bytes is used for the FDT expand size when fixing up
reserved memory node. Increase it to 1024 bytes with an estimated
size of 64 bytes per PMP memory region by 16 regions in total.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-07-06 14:05:29 +05:30
Alexandre Ghiti
6966ad0abe platform/lib: Allow the OS to map the regions that are protected by PMP
This is achieved by removing the 'no-map' property from the
'reserved-memory' node when PMP is present, otherwise we keep it as it
offers a small protection if the OS does not map this region at all.
A new callback in platform_override is introduced and allows to fixup the
device-tree. It is used here to override this new default behaviour on
SiFive Fu540 platforms that has an erratum that prevents S-mode software
to access a PMP protected region using 1GB page table mapping.

If PMP is present, telling the OS not to map the reserved regions does not
add much protection since it only avoids access to regions that are already
protected by PMP. But by not allowing the OS to map those regions, it
creates holes in the OS system memory map and prevents the use of
hugepages which would generate, among other benefits, less TLB miss.

Signed-off-by: Alexandre Ghiti <alex@ghiti.fr>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-06-15 09:25:44 +05:30
Anup Patel
a38bea9341 lib: sbi_hart: Detect number of supported PMP regions
It is not mandatory for a RISC-V systems to implement all PMP
regions so we have to check all PMPADDRx CSRs to determine excat
number of supported PMP regions.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-05-19 09:19:48 +05:30
Anup Patel
63b0f5f71a include: sbi: Use scratch pointer as parmeter in HART feature APIs
It makes more sense to have scratch pointer as parameter in
HART feature APIs because:
1. We already have scratch pointer at places where these APIs
   are used.
2. This is consistent with lot of other APIs in sbi_hart.h

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-19 09:19:42 +05:30
Atish Patra
b2df751acf platform: Move platform features to hart
PMP & performance counters belong to a hart rather than a platform.
In addition to that, these features enable reading/writing from a
particular csr. Thus, they can be detected and set at runtime rather
than compile time.

Move PMP/MCOUNTEREN/SCOUNTEREN features to hart and detect them at runtime.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-05-10 10:05:41 +05:30
Atish Patra
79d0fadb06 lib: utils: Update reserved memory fdt node even if PMP is not present
As per RISC-V ISA, pmp is not mandatory. Currently, we only add reserved
memory node in DT only if PMP is present. That allows supervisor to access
the memory where OpenSBI continue to exist without realizing it for non-pmp
based platforms. It may result in corrupting OpenSBI. That's why OpenSBI
should at least let the supervisor know where it continue to exist.
This a best effort service provided by OpenSBI expecting that supervisor
software is not buggy and properly sets up its memory after parsing the
reserved-memory device tree node.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-05-10 10:00:02 +05:30
Anup Patel
19e966b862 lib: utils: Add fdt_parse_hart_id() function
Parsing HART id from a CPU DT node is a common requirement for
RISC-V systems. The newly added fdt_parse_hart_id() also helps
reduce duplicate code between fdt_cpu_fixup() function and
fdt_parse_hart_count() function.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2020-05-01 09:43:07 +05:30
Anup Patel
160c88535f lib: utils: Improve fdt_cpu_fixup() implementation
Currently, the fdt_cpu_fixup() implementation assumes:
1. We have one CPU DT for each HART under /cpus DT node
2. The CPU DT nodes are named sequentially (i.e cpu@0,
   cpu@1, ...) which is not true for discontinuous and
   sparse HART ids (i.e. cpu@0, cpu@4, cpu@5). Generally,
   CPU DT node are named based on HART id and not HART
   index

If any of the above assumptions are violated then the
fdt_cpu_fixup() will not work.

This improves fdt_cpu_fixup() implementation and makes
it independent of above assumptions.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-03-28 13:31:50 +05:30
Atish Patra
040e4e2ec2 lib: utils: Move fdt fixup helper routines to a different file
FDT helper file contain both fdt fixup and parsing functions.

Split the fixup related functions to a separate file for a better code
organization.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-03-24 13:30:32 +05:30