Currently, we fail with error SBI_ENOTSUPP when we are not able
to handle illegal instruction trap. Instead, we should just
redirect illegal instruction trap to S-mode when not handled.
This redirection of illegal instruction trap will help lazy
save/restore of floating point registers to work correctly in
Linux kernel.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
The mtval CSR is very useful information when debugging hence
print it upon trap error in sbi_trap_error().
Signed-off-by: Anup Patel <anup.patel@wdc.com>
We generally don't get misaligned load/store traps from Linux/U-Boot
compiled using GCC 8.2 or higher but this is not true with older
GCC toolchains. To tackle this we add misaligned load/store trap
handling adopted from BBL sources but much more simpler.
(Note: BBL sources can be found at https://github.com/riscv/riscv-pk.git)
Signed-off-by: Anup Patel <anup.patel@wdc.com>
