Commit Graph

8 Commits

Author SHA1 Message Date
Xiang W
1cb792d606 lib: sbi: simplify inline function in sbi_dtbr.c
The inline function can simplify the code by setting some call
restrictions. This ensures logical smoothness

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
2024-05-13 16:50:49 +05:30
Xiang W
7b37da3cb0 lib: sbi: fix return type of sbi_dbtr_shmem_disabled
Modify the return value of the sbi_dbtr_shmem_disabled function to
bool to make the semantics clearer.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
2024-05-13 16:40:05 +05:30
Xiang W
e065c3cd5d lib: sbi: Fixed memory permission check in sbi_dbtr_setup_shmem
The previous code detected shmem_phys_hi and shmem_phys_lo as two
addresses. fix this bug

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
2024-05-13 16:39:39 +05:30
Xiang W
7f54527029 lib: sbi: fix DBTR_SHMEM_MAKE_PHYS for RV64
Obtaining a 64-bit address under rv64 does not require combining
32-bit registers

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
2024-05-13 16:38:35 +05:30
Xiang W
744f495653 lib: sbi: Removal unnecessary check dbtr_thishart_state_ptr
After getting hart_shmem_base, dbtr_thishart_state_ptr cannot be
empty. So remove check code.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
2024-05-13 16:37:56 +05:30
Xiang W
4953bd721a lib: sbi: fix hart_shmem_base
When only phys_hi is equal to SBI_DBTR_SHMEM_INVALID_ADDR, it may be
a legal address. The old code would modify the legal address.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
2024-05-13 16:35:20 +05:30
Himanshu Chauhan
1ec353d504 lib: sbi: Use mask to check the free bit during trigger allocation
The trigger allocation function uses bit shift instead of mask to check the
mapped status of the triggers. This causes index 0 to be return always. As a
result, the older triggers are overwritten.

Use the mask for MAPPED field in state word to check if the trigger is mapped.

Fixes: 97f234f15 ("lib: sbi: Introduce the SBI debug triggers extension support")
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
2024-02-05 10:23:01 +05:30
Himanshu Chauhan
97f234f15c lib: sbi: Introduce the SBI debug triggers extension support
RISC-V Debug specification includes Sdtrig ISA extension
which describes Trigger Module. Triggers can cause
a breakpoint exception or trace action without execution
of a special instruction. They can be used to implement
hardware breakpoints and watchpoints for native debugging.

The SBI Debut Trigger extension (Draft v6) can be found at:
https://lists.riscv.org/g/tech-debug/topic/99825362#1302

This patch is an initial implementation of SBI Debug
Trigger Extension (Draft v6) in OpenSBI.

The following features are supported:
 * mcontrol, mcontrol6 triggers
 * Breakpoint and trace actions

NOTE: Chained triggers are not supported

Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
2024-01-10 10:55:42 +05:30