In case the platform specific method for shutting down
the system fails (or is not implemented), at least make
sure that all harts hang instead of just the current hart.
Signed-off-by: Nick Kossifidis <mick@ics.forth.gr>
Some older toolchains may not have all the csr's defined. Update all
the csr functions to use the CSR_ #define values instead of the
toolchain defined values.
Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
csr_val is a tartget length based variable, so on 32-bit devices it's
only 32-bits. To avoid clearing the entire register perform both steps
in a single line.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Some toolchains might not have all the CSRs available (as seen with
GCC 7.2). So, instead use the defined CSR_ values.
Signed-off-by: Olof Johansson <olof@lixom.net>
Currently, the OpenSBI version is in top-level Makefile so
firmware linking to OpenSBI static library have no-way to
know OpenSBI version.
This patch moves OpenSBI version from top-level Makefile to
sbi/sbi_version.h header which provides OPENSBI_VERSION_MAJOR
and OPENSBI_VERSION_MINOR defines.
NOTE: the SBI spec (or SBI ecall interface) version is
different. The SBI spec version is provided by functions
sbi_ecall_version_major() and sbi_ecall_version_minor().
Signed-off-by: Anup Patel <anup.patel@wdc.com>
This patch updates copyright header in all files as follows:
1. Makes "SPDX-License-Identifier: BSD-2-Clause" as first line
2. Change copyright year to 2019 for Western Digital
Signed-off-by: Anup Patel <anup.patel@wdc.com>
For better naming, we rename ipi_inject() to ipi_send() in
struct sbi_platform. We also replace term "inject" with
"send" in all related places.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
It is not necessary that platform has MMIO-based timer value
register. It can also have some custom (implementation specific)
CSR for timer value.
This patch renames SBI_PLATFORM_HAS_MMIO_TIMER_VALUE to
SBI_PLATFORM_HAS_TIMER_VALUE to imply "platform timer value"
instead of "mmio timer value".
Signed-off-by: Anup Patel <anup.patel@wdc.com>
The target_hart and hartid paramter of TIMER callbacks is not
required because it always current hartid which can be obtained
using sbi_current_hartid() API.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
The hartid parameter in IRQCHIP callbacks of sbi_platform
is not required because current hartid can be determined
using sbi_current_hartid() API.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
The source_hart and hartid parameter is really not required in
IPI callbacks of sbi_platform because current hartid can always
be obtained by calling sbi_current_hartid() API.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
This patch adds doxygen style documenation for struct sbi_platform
and related functions/macros/defines.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
We don't need to pre-enable MSIP in MIE CSR when
calling sbi_init() from firmware. This patch updates
documentation accordingly.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
As per the RISC-V ISA, mideleg and medeleg registers should not exist
if S-mode is not present for a hart.
We shouldn't access these CSRs if non S-mode harts.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
S-mode software may send IPI to self. For example,
tlbflush may be executed for the same hart.
Let the hart send IPI to itself. It's an overhead
but doesn't break anything. However, if we don't
allow it, it breaks if S-mode keep sending IPIs.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
IPIs are updated in scratch space by source hart.
However, different harts or same hart may want to
send different IPIs before previous IPI was read
by the target hart. Currently, previous IPI type
is overwritten in that case.
Use atomic bit set/clear operations to update IPIs.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
The secondary hart waits for an IPI signal from the boot hart to
executing boot code (hot boot). As a result, software generated
interrupts have to be enabled for secondary harts before waiting for
the boot hart boot completion IPI signal.
Enabling software generated interrupts (IPI) can be done independently
of the firmware code and moved to libsbi code so that the different
firmware do not have to implement this.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
We should use AMO instructions whenever __riscv_atomic is
defined (i.e. atomics are supported). We use LR/SC only when
__riscv_atomic is not defined.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Use commonly accepted styles: newlines after declarations and before
return to make the code more readable.
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
This patch adds doxygen style documentation for struct sbi_trap_regs
and related macros/defines/functions.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
The patch removes redundant csr_read_n() and csr_write_n()
because same thing can be achieved by using __ASM_STR()
macro in csr_read() and csr_write() macros.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Currently, we fail with error SBI_ENOTSUPP when we are not able
to handle illegal instruction trap. Instead, we should just
redirect illegal instruction trap to S-mode when not handled.
This redirection of illegal instruction trap will help lazy
save/restore of floating point registers to work correctly in
Linux kernel.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
The mtval CSR is very useful information when debugging hence
print it upon trap error in sbi_trap_error().
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Instead of having separate timer_init() hooks for cold and
warm boot, this patch updates struct sbi_platform to have just
one timer_init() hook. The type of boot (cold or warm) is now
a boolean flag parameter for the updated timer_init() hook.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Instead of having separate ipi_init() hooks for cold and warm boot,
this patch updates struct sbi_platform to have just one ipi_init()
hook. The type of boot (cold or warm) is now a boolean flag parameter
for the updated ipi_init() hook.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Instead of having separate irqchip_init() hooks for cold and
warm boot, this patch updates struct sbi_platform to have just
one irqchip_init() hook. The type of boot (cold or warm) is now
a boolean flag parameter for the updated irqchip_init() hook.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Instead of having separate early_init() and final_init() hooks
for cold and warm boot, this patch updates struct sbi_platform
to have just one early_init() and one final_init() hook. The
type of boot (cold or warm) is now a boolean flag parameter for
the updated early_init() and final_init() hooks.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
This patch moves all ECALL defines to sbi_ecall_interface.h so
that it can be shared with firmware payloads.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
We generally don't get misaligned load/store traps from Linux/U-Boot
compiled using GCC 8.2 or higher but this is not true with older
GCC toolchains. To tackle this we add misaligned load/store trap
handling adopted from BBL sources but much more simpler.
(Note: BBL sources can be found at https://github.com/riscv/riscv-pk.git)
Signed-off-by: Anup Patel <anup.patel@wdc.com>
As of now, uboot doesn't have support for SMP.
Moreover, unleashed board has a E51 hart which
doesn't not support S mode.
We should only boot only 1 non-zero hart.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Conditionnally delegate page fault exceptions from M mode to S mode
based on the platform features.
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
The sbi_hart_switch_mode() will be used by CPU hotplug. This means
if we have prints in sbi_hart_switch_mode() then these prints will
mix with Linux prints.
Being a runtime firmware, we should be verbose only at coldboot
time and error situations.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
commit d403c70fb1 breaks Linux
booting because of fewer exceptions delegated to S-mode. This
patch fixes Linux booting by having all required exceptions
delegated to S-mode.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Avoid getting messages from multiple harts mingled into garbage text
with a spinlock serializing calls to sbi_puts() and sbi_printf().
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Cleanup sbi_hart_boot_nexti() code, adding messages for clarity and
rename the function to sbi_hart_switch_mode() to reflect what the
function actually does.
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
When S mode is not supported, simply clear mideleg and medeleg.
Otherwise, set delegation from M-mode to S-mode, removing the page
fault exceptions as those would not happen in M-mode.
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Make it clear that the end of the FW execution was reached without the
hand being passed to any payload.
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Allow a platform to report its supported features in more details.
The new features defined are:
* SBI_PLATFORM_HAS_PMP
* SBI_PLATFORM_HAS_SCOUNTEREN
* SBI_PLATFORM_HAS_MCOUNTEREN
In addition, define the macro SBI_PLATFORM_DEFAULT_FEATURES as the set
of features that are generally expected to be supported by a Linux
capable platform.
Operations touching the features controlled with these falgs are not
executed if the platform does not set the corresponding feature flags.
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
We should not jump to next stage if next mode (S-mode or U-mode)
is not supported by HART.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
On QEMU Virt, max supported HARTs are 8 but number of HARTs
actually depend on "-smp" command-line parameter passed to
QEMU. This creates problems in sbi_hart_wake_coldboot_harts()
because when number of HARTs are less than 8.
To tackle this, we introduce a bitmap to track HARTs waiting
for coldboot to finish. We wake only those HARTs who have
set their bit in coldboot bitmap.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
