platform: generic: andes/renesas: Add SBI EXT to check for enabling IOCP errata

I/O Coherence Port (IOCP) provides an AXI interface for connecting
external non-caching masters, such as DMA controllers. The accesses
from IOCP are coherent with D-Caches and L2 Cache.

IOCP is a specification option and is disabled on the Renesas RZ/Five
SoC (which is based on Andes AX45MP core) due to this reason IP blocks
using DMA will fail.

As a workaround for SoCs with IOCP disabled CMO needs to be handled by
software. Firstly OpenSBI configures the memory region as
"Memory, Non-cacheable, Bufferable" and passes this region as a global
shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA
allocations happen from this region and synchronization callbacks are
implemented to synchronize when doing DMA transactions.

SBI_EXT_ANDES_IOCP_SW_WORKAROUND checks if the IOCP errata should be
applied to handle cache management.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>

platform/generic/andes/andes_sbi.c

@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ *
+ */
+#include <andes/andes45.h>
+#include <andes/andes_sbi.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_error.h>
+
+enum sbi_ext_andes_fid {
+	SBI_EXT_ANDES_FID0 = 0, /* Reserved for future use */
+	SBI_EXT_ANDES_IOCP_SW_WORKAROUND,
+};
+
+static bool andes45_cache_controllable(void)
+{
+	return (((csr_read(CSR_MICM_CFG) & MICM_CFG_ISZ_MASK) ||
+		 (csr_read(CSR_MDCM_CFG) & MDCM_CFG_DSZ_MASK)) &&
+		(csr_read(CSR_MMSC_CFG) & MMSC_CFG_CCTLCSR_MASK) &&
+		(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_CCTL_SUEN_MASK) &&
+		misa_extension('U'));
+}
+
+static bool andes45_iocp_disabled(void)
+{
+	return (csr_read(CSR_MMSC_CFG) & MMSC_IOCP_MASK) ? false : true;
+}
+
+static bool andes45_apply_iocp_sw_workaround(void)
+{
+	return andes45_cache_controllable() & andes45_iocp_disabled();
+}
+
+int andes_sbi_vendor_ext_provider(long funcid,
+				  const struct sbi_trap_regs *regs,
+				  unsigned long *out_value,
+				  struct sbi_trap_info *out_trap,
+				  const struct fdt_match *match)
+{
+	switch (funcid) {
+	case SBI_EXT_ANDES_IOCP_SW_WORKAROUND:
+		*out_value = andes45_apply_iocp_sw_workaround();
+		break;
+
+	default:
+		return SBI_EINVAL;
+	}
+
+	return 0;
+}