lib: timer: Provide a hart based timer feature

As per the RISC-V specification, time value can be obtained from a time
CSR implemented in hardware or a MMIO based IP block. Qemu virt machine
already supports timer csr while CLINT provides the timer for other
platforms.

Implement a hart specific timer feature that can be detected at runtime.
As CSR based timer implementation are faster than MMIO address based, it
is always preferred over MMIO based one.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

include/sbi/sbi_hart.h

@@ -20,6 +20,8 @@ enum sbi_hart_features {
 	SBI_HART_HAS_SCOUNTEREN = (1 << 1),
 	/** Hart has M-mode counter enable */
 	SBI_HART_HAS_MCOUNTEREN = (1 << 2),
+	/** HART has timer csr implementation in hardware */
+	SBI_HART_HAS_TIME = (1 << 3),
 };
 
 struct sbi_scratch;