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lib: sbi: Remove redundant call to sbi_hart_expected_trap_addr()

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The variable "sbi_hart_expected_trap" has already been extern variable.
Therefore, the program can directly refer to it instead of calling
sbi_hart_expected_trap_addr().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20250703151957.2545958-2-alvinga@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Alvin Chang
2025-07-03 23:19:56 +08:00
committed by Anup Patel
parent 61083eb504
commit ea5abd1f5e
4 changed files with 7 additions and 11 deletions
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4
include/sbi/sbi_csr_detect.h
View File

@@ -18,7 +18,7 @@
({ \ ({ \
register ulong tinfo asm("a3") = (ulong)trap; \ register ulong tinfo asm("a3") = (ulong)trap; \
register ulong ttmp asm("a4"); \ register ulong ttmp asm("a4"); \
register ulong mtvec = sbi_hart_expected_trap_addr(); \ register ulong mtvec = (ulong)sbi_hart_expected_trap; \
register ulong ret = 0; \ register ulong ret = 0; \
((struct sbi_trap_info *)(trap))->cause = 0; \ ((struct sbi_trap_info *)(trap))->cause = 0; \
asm volatile( \ asm volatile( \
@@ -37,7 +37,7 @@
({ \ ({ \
register ulong tinfo asm("a3") = (ulong)trap; \ register ulong tinfo asm("a3") = (ulong)trap; \
register ulong ttmp asm("a4"); \ register ulong ttmp asm("a4"); \
register ulong mtvec = sbi_hart_expected_trap_addr(); \ register ulong mtvec = (ulong)sbi_hart_expected_trap; \
((struct sbi_trap_info *)(trap))->cause = 0; \ ((struct sbi_trap_info *)(trap))->cause = 0; \
asm volatile( \ asm volatile( \
"add %[ttmp], %[tinfo], zero\n" \ "add %[ttmp], %[tinfo], zero\n" \

4
include/sbi/sbi_hart.h
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@@ -134,10 +134,6 @@ int sbi_hart_reinit(struct sbi_scratch *scratch);
int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot); int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot);
extern void (*sbi_hart_expected_trap)(void); extern void (*sbi_hart_expected_trap)(void);
static inline ulong sbi_hart_expected_trap_addr(void)
{
return (ulong)sbi_hart_expected_trap;
}
unsigned int sbi_hart_mhpm_mask(struct sbi_scratch *scratch); unsigned int sbi_hart_mhpm_mask(struct sbi_scratch *scratch);
void sbi_hart_delegation_dump(struct sbi_scratch *scratch, void sbi_hart_delegation_dump(struct sbi_scratch *scratch,

4
lib/sbi/sbi_illegal_atomic.c
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@@ -30,7 +30,7 @@ int sbi_illegal_atomic(ulong insn, struct sbi_trap_regs *regs)
{ \ { \
register ulong tinfo asm("a3"); \ register ulong tinfo asm("a3"); \
register ulong mstatus = 0; \ register ulong mstatus = 0; \
register ulong mtvec = sbi_hart_expected_trap_addr(); \ register ulong mtvec = (ulong)sbi_hart_expected_trap; \
type ret = 0; \ type ret = 0; \
trap->cause = 0; \ trap->cause = 0; \
asm volatile( \ asm volatile( \
@@ -57,7 +57,7 @@ int sbi_illegal_atomic(ulong insn, struct sbi_trap_regs *regs)
{ \ { \
register ulong tinfo asm("a3"); \ register ulong tinfo asm("a3"); \
register ulong mstatus = 0; \ register ulong mstatus = 0; \
register ulong mtvec = sbi_hart_expected_trap_addr(); \ register ulong mtvec = (ulong)sbi_hart_expected_trap; \
type ret = 0; \ type ret = 0; \
trap->cause = 0; \ trap->cause = 0; \
asm volatile( \ asm volatile( \

6
lib/sbi/sbi_unpriv.c
View File

@@ -24,7 +24,7 @@
{ \ { \
register ulong tinfo asm("a3"); \ register ulong tinfo asm("a3"); \
register ulong mstatus = 0; \ register ulong mstatus = 0; \
register ulong mtvec = sbi_hart_expected_trap_addr(); \ register ulong mtvec = (ulong)sbi_hart_expected_trap; \
type ret = 0; \ type ret = 0; \
trap->cause = 0; \ trap->cause = 0; \
asm volatile( \ asm volatile( \
@@ -51,7 +51,7 @@
{ \ { \
register ulong tinfo asm("a3") = (ulong)trap; \ register ulong tinfo asm("a3") = (ulong)trap; \
register ulong mstatus = 0; \ register ulong mstatus = 0; \
register ulong mtvec = sbi_hart_expected_trap_addr(); \ register ulong mtvec = (ulong)sbi_hart_expected_trap; \
trap->cause = 0; \ trap->cause = 0; \
asm volatile( \ asm volatile( \
"add %[tinfo], %[taddr], zero\n" \ "add %[tinfo], %[taddr], zero\n" \
@@ -121,7 +121,7 @@ ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap)
register ulong tinfo asm("a3"); register ulong tinfo asm("a3");
register ulong ttmp asm("a4"); register ulong ttmp asm("a4");
register ulong mstatus = 0; register ulong mstatus = 0;
register ulong mtvec = sbi_hart_expected_trap_addr(); register ulong mtvec = (ulong)sbi_hart_expected_trap;
ulong insn = 0; ulong insn = 0;
trap->cause = 0; trap->cause = 0;