Firmware/opensbi
8
0
Fork 0
forked from Mirrors/opensbi
Code Pull Requests Activity

docs: platform: update platform_requirements.md

Browse Source 
"Zicsr" isa extension has been separated from "I" extension.
This patch add the isa requirement of "Zicsr" extension in
platform requirements documentation.

Signed-off-by: Yangjie Zhang <jay1273062855@outlook.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Yangjie Zhang
2023-09-28 16:25:23 +08:00
committed by Anup Patel
parent d891caeae9
commit e8114c6ae2
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
docs/platform_requirements.md
View File

@@ -18,7 +18,7 @@ Base Platform Requirements
The base RISC-V platform requirements for OpenSBI are as follows: The base RISC-V platform requirements for OpenSBI are as follows:
1. At least rv32ima or rv64ima required on all HARTs 1. At least rv32ima_zicsr or rv64ima_zicsr required on all HARTs
2. At least one HART should have S-mode support because: 2. At least one HART should have S-mode support because:
* SBI calls are meant for RISC-V S-mode (Supervisor mode) * SBI calls are meant for RISC-V S-mode (Supervisor mode)
@@ -33,7 +33,7 @@ The base RISC-V platform requirements for OpenSBI are as follows:
6. Hardware support for injecting M-mode software interrupts on 6. Hardware support for injecting M-mode software interrupts on
a multi-HART platform a multi-HART platform
The RISC-V extensions not covered by rv32ima or rv64ima are optional The RISC-V extensions not covered by rv32ima_zicsr or rv64ima_zicsr are optional
for OpenSBI. Although, OpenSBI will detect and handle some of these for OpenSBI. Although, OpenSBI will detect and handle some of these
optional RISC-V extensions at runtime. optional RISC-V extensions at runtime.