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platform: Add support for Shakti C-class SoC from IIT-M

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C-Class is a member of the SHAKTI family of processors from Indian
Institute of Technology - Madras(IIT-M).
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.

https://gitlab.com/shaktiproject/cores/c-class/blob/master/README.md

We add OpenSBI support for Shakti C-class SoC.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
Vijai Kumar K
2020-06-17 19:25:16 +05:30
committed by Anup Patel
parent 637b348224
commit db56ef367c
10 changed files with 181 additions and 0 deletions
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44
lib/utils/serial/shakti-uart.c Normal file
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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2020 Vijai Kumar K <vijai@behindbytes.com>
*/
#include <sbi/riscv_io.h>
#include <sbi/sbi_console.h>
#include <sbi_utils/serial/shakti-uart.h>
#define REG_BAUD 0x00
#define REG_TX 0x04
#define REG_RX 0x08
#define REG_STATUS 0x0C
#define REG_DELAY 0x10
#define REG_CONTROL 0x14
#define REG_INT_EN 0x18
#define REG_IQ_CYCLES 0x1C
#define REG_RX_THRES 0x20
static volatile void *uart_base;
void shakti_uart_putc(char ch)
{
while((readw(uart_base + REG_STATUS) & 0x2) == 0);
writeb(ch, uart_base + REG_TX);
}
int shakti_uart_getc(void)
{
u16 status = readw(uart_base + REG_STATUS);
if (status & 0x8)
return readb(uart_base + REG_RX);
return -1;
}
int shakti_uart_init(unsigned long base, u32 in_freq, u32 baudrate)
{
uart_base = (volatile void *)base;
u16 baud = (u16)(in_freq/(16 * baudrate));
writew(baud, uart_base + REG_BAUD);
return 0;
}