forked from Mirrors/opensbi
firmware: Rename fw_common.S to fw_base.S
The fw_common.S is the base firmware extendend by fw_jump and fw_payload. This patch renames fw_common.S to fw_base.S to have more clear/intutive name for base firmware. Signed-off-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
Anup Patel
351
firmware/fw_base.S
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351
firmware/fw_base.S
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/*
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* Copyright (c) 2018 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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.align 3
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.section .entry, "ax", %progbits
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.globl _start
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.globl _start_warm
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_start:
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/*
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* Jump to warm-boot if this is not the first core booting,
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* that is, for mhartid != 0
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*/
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csrr a6, mhartid
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blt zero, a6, _wait_for_boot_hart
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/* Zero-out BSS */
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la a4, _bss_start
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la a5, _bss_end
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_bss_zero:
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REG_S zero, (a4)
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add a4, a4, __SIZEOF_POINTER__
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blt a4, a5, _bss_zero
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/* Override pervious arg1 */
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add s0, a0, zero
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add s1, a1, zero
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call fw_prev_arg1
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add t1, a0, zero
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add a0, s0, zero
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add a1, s1, zero
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beqz t1, _prev_arg1_override_done
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add a1, t1, zero
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_prev_arg1_override_done:
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/*
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* Relocate Flatened Device Tree (FDT)
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* source FDT address = previous arg1
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* destination FDT address = next arg1
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*
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* Note: We will preserve a0 and a1 passed by
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* previous booting stage.
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*/
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beqz a1, _fdt_reloc_done
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/* Mask values in a3 and a4 */
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li a3, ~0xf
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li a4, 0xff
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/* t1 = destination FDT start address */
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add s0, a0, zero
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add s1, a1, zero
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call fw_next_arg1
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add t1, a0, zero
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add a0, s0, zero
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add a1, s1, zero
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beqz t1, _fdt_reloc_done
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and t1, t1, a3
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/* t0 = source FDT start address */
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add t0, a1, zero
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and t0, t0, a3
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/* t2 = source FDT size in big-endian */
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lwu t2, 4(t0)
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/* t3 = bit[15:8] of FDT size */
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add t3, t2, zero
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srli t3, t3, 16
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and t3, t3, a4
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slli t3, t3, 8
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/* t4 = bit[23:16] of FDT size */
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add t4, t2, zero
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srli t4, t4, 8
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and t4, t4, a4
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slli t4, t4, 16
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/* t5 = bit[31:24] of FDT size */
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add t5, t2, zero
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and t5, t5, a4
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slli t5, t5, 24
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/* t2 = bit[7:0] of FDT size */
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srli t2, t2, 24
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and t2, t2, a4
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/* t2 = FDT size in little-endian */
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or t2, t2, t3
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or t2, t2, t4
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or t2, t2, t5
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/* t2 = destination FDT end address */
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add t2, t1, t2
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/* FDT copy loop */
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ble t2, t1, _fdt_reloc_done
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_fdt_reloc_again:
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REG_L t3, 0(t0)
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REG_S t3, 0(t1)
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add t0, t0, __SIZEOF_POINTER__
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add t1, t1, __SIZEOF_POINTER__
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blt t1, t2, _fdt_reloc_again
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_fdt_reloc_done:
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/* Update boot hart flag */
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la a4, _boot_hart_done
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li a5, 1
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REG_S a5, (a4)
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j _wait_for_boot_hart
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.align 3
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_boot_hart_done:
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RISCV_PTR 0
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.align 3
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/* Wait for boot hart */
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_wait_for_boot_hart:
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la a4, _boot_hart_done
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REG_L a5, (a4)
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beqz a5, _wait_for_boot_hart
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_start_warm:
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/* Disable and clear all interrupts */
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csrw mie, zero
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csrw mip, zero
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/* Set MSIE bit to receive IPI */
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li a2, MIP_MSIP
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csrw mie, a2
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/* Preload per-HART details
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* s6 -> HART ID
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* s7 -> HART Count
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* s8 -> HART Stack Size
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*/
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csrr s6, mhartid
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la a4, platform
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lwu s7, RISCV_PLATFORM_HART_COUNT_OFFSET(a4)
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lwu s8, RISCV_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
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/* HART ID should be within expected limit */
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csrr s6, mhartid
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bge s6, s7, _start_hang
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/* Setup scratch space */
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la tp, _fw_end
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mul a5, s7, s8
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add tp, tp, a5
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mul a5, s8, s6
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sub tp, tp, a5
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li a5, RISCV_SCRATCH_SIZE
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sub tp, tp, a5
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csrw mscratch, tp
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/* Initialize scratch space */
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REG_S zero, RISCV_SCRATCH_TMP0_OFFSET(tp)
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la a4, _fw_start
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la a5, _fw_end
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mul t0, s7, s8
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add a5, a5, t0
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sub a5, a5, a4
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REG_S a4, RISCV_SCRATCH_FW_START_OFFSET(tp)
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REG_S a5, RISCV_SCRATCH_FW_SIZE_OFFSET(tp)
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/* Note: fw_next_arg1() uses a0, a1, and ra */
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call fw_next_arg1
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REG_S a0, RISCV_SCRATCH_NEXT_ARG1_OFFSET(tp)
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/* Note: fw_next_addr() uses a0, a1, and ra */
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call fw_next_addr
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REG_S a0, RISCV_SCRATCH_NEXT_ADDR_OFFSET(tp)
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li a4, PRV_S
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REG_S a4, RISCV_SCRATCH_NEXT_MODE_OFFSET(tp)
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la a4, _start_warm
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REG_S a4, RISCV_SCRATCH_WARMBOOT_ADDR_OFFSET(tp)
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la a4, platform
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REG_S a4, RISCV_SCRATCH_PLATFORM_ADDR_OFFSET(tp)
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la a4, _hartid_to_scratch
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REG_S a4, RISCV_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp)
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REG_S zero, RISCV_SCRATCH_IPI_TYPE_OFFSET(tp)
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/* Setup stack */
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add sp, tp, zero
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/* Setup trap handler */
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la a4, _trap_handler
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csrw mtvec, a4
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/* Initialize SBI runtime */
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csrr a0, mscratch
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call sbi_init
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/* We don't expect to reach here hence just hang */
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j _start_hang
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.align 3
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.section .entry, "ax", %progbits
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.globl _hartid_to_scratch
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_hartid_to_scratch:
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add sp, sp, -(3 * __SIZEOF_POINTER__)
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REG_S s0, (sp)
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REG_S s1, (__SIZEOF_POINTER__)(sp)
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REG_S s2, (__SIZEOF_POINTER__ * 2)(sp)
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/*
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* a0 -> HART ID (passed by caller)
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* s0 -> HART Stack Size
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* s1 -> HART Stack End
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* s2 -> Temporary
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*/
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la s2, platform
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lwu s0, RISCV_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
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lwu s2, RISCV_PLATFORM_HART_COUNT_OFFSET(s2)
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mul s2, s2, s0
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la s1, _fw_end
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add s1, s1, s2
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mul s2, s0, a0
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sub s1, s1, s2
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li s2, RISCV_SCRATCH_SIZE
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sub a0, s1, s2
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REG_L s0, (sp)
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REG_L s1, (__SIZEOF_POINTER__)(sp)
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REG_L s2, (__SIZEOF_POINTER__ * 2)(sp)
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add sp, sp, (3 * __SIZEOF_POINTER__)
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ret
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.align 3
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.section .entry, "ax", %progbits
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.globl _start_hang
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_start_hang:
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wfi
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j _start_hang
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.align 3
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.section .entry, "ax", %progbits
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.globl _trap_handler
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_trap_handler:
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/* Swap SP and MSCRATCH */
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csrrw sp, mscratch, sp
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/* Setup exception stack */
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add sp, sp, -(RISCV_TRAP_REGS_SIZE)
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/* Save RA, T0, T1, and T2 */
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REG_S ra, RISCV_TRAP_REGS_OFFSET(ra)(sp)
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REG_S t0, RISCV_TRAP_REGS_OFFSET(t0)(sp)
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REG_S t1, RISCV_TRAP_REGS_OFFSET(t1)(sp)
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REG_S t2, RISCV_TRAP_REGS_OFFSET(t2)(sp)
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/* Save original SP and restore MSCRATCH */
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add t0, sp, RISCV_TRAP_REGS_SIZE
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csrrw t0, mscratch, t0
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REG_S t0, RISCV_TRAP_REGS_OFFSET(sp)(sp)
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/* Save MEPC and MSTATUS CSRs */
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csrr t0, mepc
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csrr t1, mstatus
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/*
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* Note: Fast path trap handling can be done here
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* using SP, RA, T0, T1, and T2 registers where
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* T0 <- MEPC
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* T1 <- MSTATUS
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*/
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/* Save MEPC and MSTATUS CSRs */
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REG_S t0, RISCV_TRAP_REGS_OFFSET(mepc)(sp)
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REG_S t1, RISCV_TRAP_REGS_OFFSET(mstatus)(sp)
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/* Save all general regisers except SP, RA, T0, T1, and T2 */
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REG_S zero, RISCV_TRAP_REGS_OFFSET(zero)(sp)
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REG_S gp, RISCV_TRAP_REGS_OFFSET(gp)(sp)
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REG_S tp, RISCV_TRAP_REGS_OFFSET(tp)(sp)
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REG_S s0, RISCV_TRAP_REGS_OFFSET(s0)(sp)
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REG_S s1, RISCV_TRAP_REGS_OFFSET(s1)(sp)
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REG_S a0, RISCV_TRAP_REGS_OFFSET(a0)(sp)
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REG_S a1, RISCV_TRAP_REGS_OFFSET(a1)(sp)
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REG_S a2, RISCV_TRAP_REGS_OFFSET(a2)(sp)
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REG_S a3, RISCV_TRAP_REGS_OFFSET(a3)(sp)
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REG_S a4, RISCV_TRAP_REGS_OFFSET(a4)(sp)
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REG_S a5, RISCV_TRAP_REGS_OFFSET(a5)(sp)
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REG_S a6, RISCV_TRAP_REGS_OFFSET(a6)(sp)
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REG_S a7, RISCV_TRAP_REGS_OFFSET(a7)(sp)
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REG_S s2, RISCV_TRAP_REGS_OFFSET(s2)(sp)
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REG_S s3, RISCV_TRAP_REGS_OFFSET(s3)(sp)
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REG_S s4, RISCV_TRAP_REGS_OFFSET(s4)(sp)
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REG_S s5, RISCV_TRAP_REGS_OFFSET(s5)(sp)
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REG_S s6, RISCV_TRAP_REGS_OFFSET(s6)(sp)
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REG_S s7, RISCV_TRAP_REGS_OFFSET(s7)(sp)
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REG_S s8, RISCV_TRAP_REGS_OFFSET(s8)(sp)
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REG_S s9, RISCV_TRAP_REGS_OFFSET(s9)(sp)
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REG_S s10, RISCV_TRAP_REGS_OFFSET(s10)(sp)
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REG_S s11, RISCV_TRAP_REGS_OFFSET(s11)(sp)
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REG_S t3, RISCV_TRAP_REGS_OFFSET(t3)(sp)
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REG_S t4, RISCV_TRAP_REGS_OFFSET(t4)(sp)
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REG_S t5, RISCV_TRAP_REGS_OFFSET(t5)(sp)
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REG_S t6, RISCV_TRAP_REGS_OFFSET(t6)(sp)
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/* Call C routine */
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add a0, sp, zero
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csrr a1, mscratch
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call sbi_trap_handler
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/* Restore all general regisers except SP, RA, T0, T1, T2, and T3 */
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REG_L gp, RISCV_TRAP_REGS_OFFSET(gp)(sp)
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REG_L tp, RISCV_TRAP_REGS_OFFSET(tp)(sp)
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REG_L s0, RISCV_TRAP_REGS_OFFSET(s0)(sp)
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REG_L s1, RISCV_TRAP_REGS_OFFSET(s1)(sp)
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REG_L a0, RISCV_TRAP_REGS_OFFSET(a0)(sp)
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REG_L a1, RISCV_TRAP_REGS_OFFSET(a1)(sp)
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REG_L a2, RISCV_TRAP_REGS_OFFSET(a2)(sp)
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REG_L a3, RISCV_TRAP_REGS_OFFSET(a3)(sp)
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REG_L a4, RISCV_TRAP_REGS_OFFSET(a4)(sp)
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REG_L a5, RISCV_TRAP_REGS_OFFSET(a5)(sp)
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REG_L a6, RISCV_TRAP_REGS_OFFSET(a6)(sp)
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REG_L a7, RISCV_TRAP_REGS_OFFSET(a7)(sp)
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REG_L s2, RISCV_TRAP_REGS_OFFSET(s2)(sp)
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REG_L s3, RISCV_TRAP_REGS_OFFSET(s3)(sp)
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REG_L s4, RISCV_TRAP_REGS_OFFSET(s4)(sp)
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REG_L s5, RISCV_TRAP_REGS_OFFSET(s5)(sp)
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REG_L s6, RISCV_TRAP_REGS_OFFSET(s6)(sp)
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REG_L s7, RISCV_TRAP_REGS_OFFSET(s7)(sp)
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REG_L s8, RISCV_TRAP_REGS_OFFSET(s8)(sp)
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REG_L s9, RISCV_TRAP_REGS_OFFSET(s9)(sp)
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REG_L s10, RISCV_TRAP_REGS_OFFSET(s10)(sp)
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REG_L s11, RISCV_TRAP_REGS_OFFSET(s11)(sp)
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REG_L t3, RISCV_TRAP_REGS_OFFSET(t3)(sp)
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REG_L t4, RISCV_TRAP_REGS_OFFSET(t4)(sp)
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REG_L t5, RISCV_TRAP_REGS_OFFSET(t5)(sp)
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REG_L t6, RISCV_TRAP_REGS_OFFSET(t6)(sp)
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/* Load T0 and T1 with MEPC and MSTATUS */
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REG_L t0, RISCV_TRAP_REGS_OFFSET(mepc)(sp)
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REG_L t1, RISCV_TRAP_REGS_OFFSET(mstatus)(sp)
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/*
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* Note: Jump here after fast trap handling
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* using SP, RA, T0, T1, and T2
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* T0 <- MEPC
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* T1 <- MSTATUS
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*/
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/* Restore MEPC and MSTATUS CSRs */
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csrw mepc, t0
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csrw mstatus, t1
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/* Restore RA, T0, T1, and T2 */
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REG_L ra, RISCV_TRAP_REGS_OFFSET(ra)(sp)
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REG_L t0, RISCV_TRAP_REGS_OFFSET(t0)(sp)
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REG_L t1, RISCV_TRAP_REGS_OFFSET(t1)(sp)
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REG_L t2, RISCV_TRAP_REGS_OFFSET(t2)(sp)
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/* Restore SP */
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REG_L sp, RISCV_TRAP_REGS_OFFSET(sp)(sp)
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mret
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