lib: utils/irqchip: Add shared MMIO region for PLIC in root domain

On platforms with Smepmp, the MMIO regions accessed by M-mode need
to be explicitly marked with M-mode only read/write or shared (both
(M-mode and S-mode) read/write permission.

If the above is not done then runtime PLIC access from M-mode on
platforms with Smepmp will result in access fault when further
results in CPU hotplug not working.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
This commit is contained in:
Anup Patel
2023-12-11 14:07:56 +05:30
committed by Anup Patel
parent 80169b25f8
commit cdebae2cc9
9 changed files with 21 additions and 1 deletions

View File

@@ -19,6 +19,8 @@
#include <sbi_utils/timer/aclint_mtimer.h>
#define PLATFORM_PLIC_ADDR 0xc000000
#define PLATFORM_PLIC_SIZE (0x200000 + \
(PLATFORM_HART_COUNT * 0x1000))
#define PLATFORM_PLIC_NUM_SOURCES 128
#define PLATFORM_HART_COUNT 4
#define PLATFORM_CLINT_ADDR 0x2000000
@@ -33,6 +35,7 @@
static struct plic_data plic = {
.addr = PLATFORM_PLIC_ADDR,
.size = PLATFORM_PLIC_SIZE,
.num_src = PLATFORM_PLIC_NUM_SOURCES,
};