forked from Mirrors/opensbi
lib: sbi: Add support for Supervisor Software Events extension
This extension [1] allows to deliver events from SBI to supervisor via a software mechanism. This extension defines events (either local or global) which are signaled by the SBI on specific signal sources (IRQ, exceptions, etc) and are injected to be executed in supervisor mode. [1] https://lists.riscv.org/g/tech-prs/message/798 Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
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Anup Patel

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commit
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@@ -33,6 +33,7 @@
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#define SBI_EXT_SUSP 0x53555350
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#define SBI_EXT_CPPC 0x43505043
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#define SBI_EXT_DBTR 0x44425452
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#define SBI_EXT_SSE 0x535345
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/* SBI function IDs for BASE extension*/
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#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
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@@ -304,6 +305,80 @@ enum sbi_cppc_reg_id {
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SBI_CPPC_NON_ACPI_LAST = SBI_CPPC_TRANSITION_LATENCY,
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};
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/* SBI Function IDs for SSE extension */
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#define SBI_EXT_SSE_READ_ATTR 0x00000000
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#define SBI_EXT_SSE_WRITE_ATTR 0x00000001
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#define SBI_EXT_SSE_REGISTER 0x00000002
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#define SBI_EXT_SSE_UNREGISTER 0x00000003
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#define SBI_EXT_SSE_ENABLE 0x00000004
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#define SBI_EXT_SSE_DISABLE 0x00000005
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#define SBI_EXT_SSE_COMPLETE 0x00000006
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#define SBI_EXT_SSE_INJECT 0x00000007
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/* SBI SSE Event Attributes. */
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enum sbi_sse_attr_id {
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SBI_SSE_ATTR_STATUS = 0x00000000,
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SBI_SSE_ATTR_PRIO = 0x00000001,
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SBI_SSE_ATTR_CONFIG = 0x00000002,
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SBI_SSE_ATTR_PREFERRED_HART = 0x00000003,
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SBI_SSE_ATTR_ENTRY_PC = 0x00000004,
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SBI_SSE_ATTR_ENTRY_ARG = 0x00000005,
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SBI_SSE_ATTR_INTERRUPTED_SEPC = 0x00000006,
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SBI_SSE_ATTR_INTERRUPTED_FLAGS = 0x00000007,
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SBI_SSE_ATTR_INTERRUPTED_A6 = 0x00000008,
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SBI_SSE_ATTR_INTERRUPTED_A7 = 0x00000009,
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SBI_SSE_ATTR_MAX = 0x0000000A
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};
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#define SBI_SSE_ATTR_STATUS_STATE_OFFSET 0
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#define SBI_SSE_ATTR_STATUS_STATE_MASK 0x3
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#define SBI_SSE_ATTR_STATUS_PENDING_OFFSET 2
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#define SBI_SSE_ATTR_STATUS_INJECT_OFFSET 3
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#define SBI_SSE_ATTR_CONFIG_ONESHOT (1 << 0)
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#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_STATUS_SPP BIT(0)
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#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_STATUS_SPIE BIT(1)
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#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_HSTATUS_SPV BIT(2)
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#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_HSTATUS_SPVP BIT(3)
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enum sbi_sse_state {
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SBI_SSE_STATE_UNUSED = 0,
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SBI_SSE_STATE_REGISTERED = 1,
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SBI_SSE_STATE_ENABLED = 2,
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SBI_SSE_STATE_RUNNING = 3,
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};
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/* SBI SSE Event IDs. */
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#define SBI_SSE_EVENT_LOCAL_RAS 0x00000000
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#define SBI_SSE_EVENT_LOCAL_PLAT_0_START 0x00004000
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#define SBI_SSE_EVENT_LOCAL_PLAT_0_END 0x00007fff
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#define SBI_SSE_EVENT_GLOBAL_RAS 0x00008000
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#define SBI_SSE_EVENT_GLOBAL_PLAT_0_START 0x00004000
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#define SBI_SSE_EVENT_GLOBAL_PLAT_0_END 0x00007fff
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#define SBI_SSE_EVENT_LOCAL_PMU 0x00010000
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#define SBI_SSE_EVENT_LOCAL_PLAT_1_START 0x00014000
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#define SBI_SSE_EVENT_LOCAL_PLAT_1_END 0x00017fff
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#define SBI_SSE_EVENT_GLOBAL_PLAT_1_START 0x0001c000
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#define SBI_SSE_EVENT_GLOBAL_PLAT_1_END 0x0001ffff
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#define SBI_SSE_EVENT_LOCAL_PLAT_2_START 0x00024000
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#define SBI_SSE_EVENT_LOCAL_PLAT_2_END 0x00027fff
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#define SBI_SSE_EVENT_GLOBAL_PLAT_2_START 0x0002c000
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#define SBI_SSE_EVENT_GLOBAL_PLAT_2_END 0x0002ffff
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#define SBI_SSE_EVENT_LOCAL_SOFTWARE 0xffff0000
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#define SBI_SSE_EVENT_LOCAL_PLAT_3_START 0xffff4000
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#define SBI_SSE_EVENT_LOCAL_PLAT_3_END 0xffff7fff
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#define SBI_SSE_EVENT_GLOBAL_SOFTWARE 0xffff8000
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#define SBI_SSE_EVENT_GLOBAL_PLAT_3_START 0xffffc000
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#define SBI_SSE_EVENT_GLOBAL_PLAT_3_END 0xffffffff
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#define SBI_SSE_EVENT_GLOBAL_BIT (1 << 15)
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#define SBI_SSE_EVENT_PLATFORM_BIT (1 << 14)
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/* SBI base specification related macros */
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#define SBI_SPEC_VERSION_MAJOR_OFFSET 24
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#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
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@@ -324,8 +399,10 @@ enum sbi_cppc_reg_id {
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#define SBI_ERR_ALREADY_STARTED -7
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#define SBI_ERR_ALREADY_STOPPED -8
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#define SBI_ERR_NO_SHMEM -9
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#define SBI_ERR_INVALID_STATE -10
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#define SBI_ERR_BAD_RANGE -11
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#define SBI_LAST_ERR SBI_ERR_NO_SHMEM
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#define SBI_LAST_ERR SBI_ERR_BAD_RANGE
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/* clang-format on */
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