forked from Mirrors/opensbi
platform: generic: renesas: rzfive: Add support to configure the PMA
I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason IP blocks using DMA will fail. The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) block that allows dynamic adjustment of memory attributes in the runtime. It contains a configurable amount of PMA entries implemented as CSR registers to control the attributes of memory locations in interest. Below are the memory attributes supported: * Device, Non-bufferable * Device, bufferable * Memory, Non-cacheable, Non-bufferable * Memory, Non-cacheable, Bufferable * Memory, Write-back, No-allocate * Memory, Write-back, Read-allocate * Memory, Write-back, Write-allocate * Memory, Write-back, Read and Write-allocate More info about PMA (section 10.3): Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. Example PMA region passed as a DT node from OpenSBI: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Lad Prabhakar
committed by
Anup Patel
Anup Patel
parent
31b82e0d50
commit
c10095132a
5
platform/generic/andes/Kconfig
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5
platform/generic/andes/Kconfig
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@@ -0,0 +1,5 @@
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# SPDX-License-Identifier: BSD-2-Clause
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config ANDES45_PMA
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bool "Andes PMA support"
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default n
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350
platform/generic/andes/andes45-pma.c
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350
platform/generic/andes/andes45-pma.c
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@@ -0,0 +1,350 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*
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* Copyright (c) 2020 Andes Technology Corporation
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*
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* Authors:
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* Nick Hu <nickhu@andestech.com>
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* Nylon Chen <nylon7@andestech.com>
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* Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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*/
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#include <andes/andes45_pma.h>
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#include <libfdt.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_error.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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/* Configuration Registers */
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#define ANDES45_CSR_MMSC_CFG 0xFC2
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#define ANDES45_CSR_MMSC_PPMA_OFFSET (1 << 30)
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#define ANDES45_PMAADDR_0 0xBD0
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#define ANDES45_PMACFG_0 0xBC0
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static inline unsigned long andes45_pma_read_cfg(unsigned int pma_cfg_off)
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{
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#define switchcase_pma_cfg_read(__pma_cfg_off, __val) \
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case __pma_cfg_off: \
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__val = csr_read(__pma_cfg_off); \
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break;
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#define switchcase_pma_cfg_read_2(__pma_cfg_off, __val) \
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switchcase_pma_cfg_read(__pma_cfg_off + 0, __val) \
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switchcase_pma_cfg_read(__pma_cfg_off + 2, __val)
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unsigned long ret = 0;
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switch (pma_cfg_off) {
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switchcase_pma_cfg_read_2(ANDES45_PMACFG_0, ret)
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default:
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sbi_panic("%s: Unknown PMA CFG offset %#x", __func__, pma_cfg_off);
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break;
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}
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return ret;
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#undef switchcase_pma_cfg_read_2
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#undef switchcase_pma_cfg_read
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}
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static inline void andes45_pma_write_cfg(unsigned int pma_cfg_off, unsigned long val)
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{
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#define switchcase_pma_cfg_write(__pma_cfg_off, __val) \
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case __pma_cfg_off: \
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csr_write(__pma_cfg_off, __val); \
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break;
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#define switchcase_pma_cfg_write_2(__pma_cfg_off, __val) \
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switchcase_pma_cfg_write(__pma_cfg_off + 0, __val) \
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switchcase_pma_cfg_write(__pma_cfg_off + 2, __val)
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switch (pma_cfg_off) {
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switchcase_pma_cfg_write_2(ANDES45_PMACFG_0, val)
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default:
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sbi_panic("%s: Unknown PMA CFG offset %#x", __func__, pma_cfg_off);
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break;
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}
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#undef switchcase_pma_cfg_write_2
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#undef switchcase_pma_cfg_write
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}
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static inline void andes45_pma_write_addr(unsigned int pma_addr_off, unsigned long val)
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{
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#define switchcase_pma_write(__pma_addr_off, __val) \
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case __pma_addr_off: \
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csr_write(__pma_addr_off, __val); \
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break;
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#define switchcase_pma_write_2(__pma_addr_off, __val) \
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switchcase_pma_write(__pma_addr_off + 0, __val) \
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switchcase_pma_write(__pma_addr_off + 1, __val)
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#define switchcase_pma_write_4(__pma_addr_off, __val) \
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switchcase_pma_write_2(__pma_addr_off + 0, __val) \
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switchcase_pma_write_2(__pma_addr_off + 2, __val)
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#define switchcase_pma_write_8(__pma_addr_off, __val) \
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switchcase_pma_write_4(__pma_addr_off + 0, __val) \
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switchcase_pma_write_4(__pma_addr_off + 4, __val)
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#define switchcase_pma_write_16(__pma_addr_off, __val) \
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switchcase_pma_write_8(__pma_addr_off + 0, __val) \
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switchcase_pma_write_8(__pma_addr_off + 8, __val)
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switch (pma_addr_off) {
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switchcase_pma_write_16(ANDES45_PMAADDR_0, val)
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default:
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sbi_panic("%s: Unknown PMA ADDR offset %#x", __func__, pma_addr_off);
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break;
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}
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#undef switchcase_pma_write_16
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#undef switchcase_pma_write_8
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#undef switchcase_pma_write_4
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#undef switchcase_pma_write_2
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#undef switchcase_pma_write
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}
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static inline unsigned long andes45_pma_read_addr(unsigned int pma_addr_off)
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{
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#define switchcase_pma_read(__pma_addr_off, __val) \
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case __pma_addr_off: \
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__val = csr_read(__pma_addr_off); \
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break;
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#define switchcase_pma_read_2(__pma_addr_off, __val) \
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switchcase_pma_read(__pma_addr_off + 0, __val) \
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switchcase_pma_read(__pma_addr_off + 1, __val)
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#define switchcase_pma_read_4(__pma_addr_off, __val) \
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switchcase_pma_read_2(__pma_addr_off + 0, __val) \
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switchcase_pma_read_2(__pma_addr_off + 2, __val)
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#define switchcase_pma_read_8(__pma_addr_off, __val) \
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switchcase_pma_read_4(__pma_addr_off + 0, __val) \
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switchcase_pma_read_4(__pma_addr_off + 4, __val)
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#define switchcase_pma_read_16(__pma_addr_off, __val) \
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switchcase_pma_read_8(__pma_addr_off + 0, __val) \
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switchcase_pma_read_8(__pma_addr_off + 8, __val)
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unsigned long ret = 0;
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switch (pma_addr_off) {
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switchcase_pma_read_16(ANDES45_PMAADDR_0, ret)
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default:
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sbi_panic("%s: Unknown PMA ADDR offset %#x", __func__, pma_addr_off);
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break;
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}
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return ret;
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#undef switchcase_pma_read_16
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#undef switchcase_pma_read_8
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#undef switchcase_pma_read_4
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#undef switchcase_pma_read_2
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#undef switchcase_pma_read
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}
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static unsigned long
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andes45_pma_setup(const struct andes45_pma_region *pma_region,
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unsigned int entry_id)
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{
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unsigned long size = pma_region->size;
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unsigned long addr = pma_region->pa;
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unsigned int pma_cfg_addr;
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unsigned long pmacfg_val;
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unsigned long pmaaddr;
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char *pmaxcfg;
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/* Check for 4KiB granularity */
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if (size < (1 << 12))
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return SBI_EINVAL;
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/* Check size is power of 2 */
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if (size & (size - 1))
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return SBI_EINVAL;
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if (entry_id > 15)
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return SBI_EINVAL;
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if (!(pma_region->flags & ANDES45_PMACFG_ETYP_NAPOT))
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return SBI_EINVAL;
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if ((addr & (size - 1)) != 0)
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return SBI_EINVAL;
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pma_cfg_addr = entry_id / 8 ? ANDES45_PMACFG_0 + 2 : ANDES45_PMACFG_0;
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pmacfg_val = andes45_pma_read_cfg(pma_cfg_addr);
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pmaxcfg = (char *)&pmacfg_val + (entry_id % 8);
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*pmaxcfg = 0;
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*pmaxcfg = pma_region->flags;
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andes45_pma_write_cfg(pma_cfg_addr, pmacfg_val);
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pmaaddr = (addr >> 2) + (size >> 3) - 1;
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andes45_pma_write_addr(ANDES45_PMAADDR_0 + entry_id, pmaaddr);
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return andes45_pma_read_addr(ANDES45_PMAADDR_0 + entry_id) == pmaaddr ?
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pmaaddr : SBI_EINVAL;
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}
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static int andes45_fdt_pma_resv(void *fdt, const struct andes45_pma_region *pma,
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unsigned int index, int parent)
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{
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int na = fdt_address_cells(fdt, 0);
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int ns = fdt_size_cells(fdt, 0);
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static bool dma_default = false;
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fdt32_t addr_high, addr_low;
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fdt32_t size_high, size_low;
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int subnode, err;
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fdt32_t reg[4];
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fdt32_t *val;
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char name[32];
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addr_high = (u64)pma->pa >> 32;
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addr_low = pma->pa;
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size_high = (u64)pma->size >> 32;
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size_low = pma->size;
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if (na > 1 && addr_high)
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sbi_snprintf(name, sizeof(name),
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"pma_resv%d@%x,%x", index,
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addr_high, addr_low);
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else
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sbi_snprintf(name, sizeof(name),
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"pma_resv%d@%x", index,
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addr_low);
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subnode = fdt_add_subnode(fdt, parent, name);
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if (subnode < 0)
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return subnode;
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if (pma->shared_dma) {
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err = fdt_setprop_string(fdt, subnode, "compatible", "shared-dma-pool");
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if (err < 0)
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return err;
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}
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if (pma->no_map) {
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err = fdt_setprop_empty(fdt, subnode, "no-map");
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if (err < 0)
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return err;
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}
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/* Linux allows single linux,dma-default region. */
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if (pma->dma_default) {
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if (dma_default)
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return SBI_EINVAL;
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err = fdt_setprop_empty(fdt, subnode, "linux,dma-default");
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if (err < 0)
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return err;
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dma_default = true;
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}
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/* encode the <reg> property value */
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val = reg;
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if (na > 1)
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*val++ = cpu_to_fdt32(addr_high);
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*val++ = cpu_to_fdt32(addr_low);
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if (ns > 1)
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*val++ = cpu_to_fdt32(size_high);
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*val++ = cpu_to_fdt32(size_low);
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err = fdt_setprop(fdt, subnode, "reg", reg,
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(na + ns) * sizeof(fdt32_t));
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if (err < 0)
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return err;
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return 0;
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}
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static int andes45_fdt_reserved_memory_fixup(void *fdt,
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const struct andes45_pma_region *pma,
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unsigned int entry)
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{
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int parent;
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/* try to locate the reserved memory node */
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parent = fdt_path_offset(fdt, "/reserved-memory");
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if (parent < 0) {
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int na = fdt_address_cells(fdt, 0);
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int ns = fdt_size_cells(fdt, 0);
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int err;
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/* if such node does not exist, create one */
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parent = fdt_add_subnode(fdt, 0, "reserved-memory");
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if (parent < 0)
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return parent;
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err = fdt_setprop_empty(fdt, parent, "ranges");
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if (err < 0)
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return err;
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err = fdt_setprop_u32(fdt, parent, "#size-cells", ns);
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if (err < 0)
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return err;
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err = fdt_setprop_u32(fdt, parent, "#address-cells", na);
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if (err < 0)
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return err;
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}
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return andes45_fdt_pma_resv(fdt, pma, entry, parent);
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}
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int andes45_pma_setup_regions(const struct andes45_pma_region *pma_regions,
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unsigned int pma_regions_count)
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{
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unsigned long mmsc = csr_read(ANDES45_CSR_MMSC_CFG);
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unsigned int dt_populate_cnt;
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unsigned int i, j;
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unsigned long pa;
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void *fdt;
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int ret;
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if (!pma_regions || !pma_regions_count)
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return 0;
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if (pma_regions_count > ANDES45_MAX_PMA_REGIONS)
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return SBI_EINVAL;
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if ((mmsc & ANDES45_CSR_MMSC_PPMA_OFFSET) == 0)
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return SBI_ENOTSUPP;
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/* Configure the PMA regions */
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for (i = 0; i < pma_regions_count; i++) {
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pa = andes45_pma_setup(&pma_regions[i], i);
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if (pa == SBI_EINVAL)
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return SBI_EINVAL;
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}
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dt_populate_cnt = 0;
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for (i = 0; i < pma_regions_count; i++) {
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if (!pma_regions[i].dt_populate)
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continue;
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dt_populate_cnt++;
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}
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if (!dt_populate_cnt)
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return 0;
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fdt = fdt_get_address();
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ret = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + (64 * dt_populate_cnt));
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if (ret < 0)
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return ret;
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for (i = 0, j = 0; i < pma_regions_count; i++) {
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if (!pma_regions[i].dt_populate)
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continue;
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ret = andes45_fdt_reserved_memory_fixup(fdt, &pma_regions[i], j++);
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if (ret)
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return ret;
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}
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return 0;
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}
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@@ -4,3 +4,5 @@
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carray-platform_override_modules-$(CONFIG_PLATFORM_ANDES_AE350) += andes_ae350
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platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
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platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
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