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Add support for Ariane FPGA SoC

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This patch adds support for Ariane platform.
We needed to enable PLIC interrupts early(like on BBL) due to some issue of the design.
Otherwise, Linux would not get any external interrupts.

Signed-off-by: Panagiotis Peristerakis <perister@ics.forth.gr>
This commit is contained in:
Panagiotis Peristerakis
2019-06-28 16:51:52 +03:00
committed by Anup Patel
parent c6d06a9448
commit b44e844880
3 changed files with 250 additions and 0 deletions
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41
platform/ariane-fpga/config.mk Normal file
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#
# SPDX-License-Identifier: GPL-2.0
#
# Copyright (C) 2019 FORTH-ICS/CARV
# Panagiotis Peristerakis <perister@ics.forth.gr>
#
#for more infos, check out /platform/template/config.mk
PLATFORM_RISCV_XLEN = 64
# Common drivers to enable
PLATFORM_SERIAL_UART8250=y
PLATFORM_IRQCHIP_PLIC=y
PLATFORM_SYS_CLINT=y
# Blobs to build
FW_TEXT_START=0x80000000
FW_JUMP=n
ifeq ($(PLATFORM_RISCV_XLEN), 32)
# This needs to be 4MB aligned for 32-bit support
FW_JUMP_ADDR=0x80400000
else
# This needs to be 2MB aligned for 64-bit support
FW_JUMP_ADDR=0x80200000
endif
FW_JUMP_FDT_ADDR=0x82200000
# Firmware with payload configuration.
FW_PAYLOAD=y
ifeq ($(PLATFORM_RISCV_XLEN), 32)
# This needs to be 4MB aligned for 32-bit support
FW_PAYLOAD_OFFSET=0x400000
else
# This needs to be 2MB aligned for 64-bit support
FW_PAYLOAD_OFFSET=0x200000
endif
FW_PAYLOAD_FDT_ADDR=0x82200000
FW_PAYLOAD_ALIGN=0x1000