forked from Mirrors/opensbi
lib: No need to set VSSTATUS.MXR bit in get_insn()
We don't need to set VSSTATUS.MXR bit in get_insn() for unpriv instruction read because MSTATUS.MXR bit applies to both "Stage1" and "Stage2" page tables. This also allows us to remove the "virt" parameter of get_insn() function. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
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@@ -29,12 +29,7 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
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struct unpriv_trap uptrap;
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ulong addr = csr_read(CSR_MTVAL);
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int i, fp = 0, shift = 0, len = 0;
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#if __riscv_xlen == 32
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bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
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#else
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bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
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#endif
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ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap);
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ulong insn = get_insn(regs->mepc, scratch, &uptrap);
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if (uptrap.cause)
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return sbi_trap_redirect(regs, scratch, regs->mepc,
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@@ -136,12 +131,7 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
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struct unpriv_trap uptrap;
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ulong addr = csr_read(CSR_MTVAL);
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int i, len = 0;
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#if __riscv_xlen == 32
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bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
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#else
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bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
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#endif
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ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap);
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ulong insn = get_insn(regs->mepc, scratch, &uptrap);
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if (uptrap.cause)
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return sbi_trap_redirect(regs, scratch, regs->mepc,
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