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lib: No need to set VSSTATUS.MXR bit in get_insn()

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We don't need to set VSSTATUS.MXR bit in get_insn() for
unpriv instruction read because MSTATUS.MXR bit applies
to both "Stage1" and "Stage2" page tables.

This also allows us to remove the "virt" parameter of
get_insn() function.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
This commit is contained in:
Anup Patel
2019-11-16 16:38:53 +05:30
committed by Anup Patel
parent 838657c052
commit b1d8c988bc
4 changed files with 6 additions and 27 deletions
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10
lib/sbi/riscv_unpriv.c
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@@ -101,10 +101,10 @@ void store_u64(u64 *addr, u64 val,
}
#endif
ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
ulong get_insn(ulong mepc, struct sbi_scratch *scratch,
struct unpriv_trap *trap)
{
ulong __mstatus = 0, __vsstatus = 0, val = 0;
ulong __mstatus = 0, val = 0;
#ifdef __riscv_compressed
ulong rvc_mask = 3, tmp;
#endif
@@ -113,9 +113,6 @@ ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
trap->tval = 0;
sbi_hart_set_trap_info(scratch, trap);
if (virt)
__vsstatus = csr_read_set(CSR_VSSTATUS, SSTATUS_MXR);
#ifndef __riscv_compressed
asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
".option push\n"
@@ -149,9 +146,6 @@ ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
[rvc_mask] "r"(rvc_mask));
#endif
if (virt)
csr_write(CSR_VSSTATUS, __vsstatus);
sbi_hart_set_trap_info(scratch, NULL);
switch (trap->cause) {
case CAUSE_LOAD_ACCESS: