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lib: utils/irqchip: plic: Allow enabling IRQs by default

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Unlike other platforms, Ariane and OpenPiton enable all IRQs by default.
This was described in commit b44e844880 ("Add support for Ariane FPGA
SoC") as "due to some issue of the design." Add this workaround behind a
flag in plic_warm_irqchip_init(), so every platform can use the same
warm init function.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Samuel Holland
2024-11-04 20:10:02 -08:00
committed by Anup Patel
parent 86d2c1797a
commit a786aed08d
4 changed files with 21 additions and 53 deletions
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25
platform/fpga/ariane/platform.c
View File

@@ -39,6 +39,7 @@ static struct plic_data plic = {
.addr = ARIANE_PLIC_ADDR,
.size = ARIANE_PLIC_SIZE,
.num_src = ARIANE_PLIC_NUM_SOURCES,
.flags = PLIC_FLAG_ARIANE_BUG,
};
static struct aclint_mswi_data mswi = {
@@ -93,27 +94,6 @@ static int ariane_final_init(bool cold_boot)
return 0;
}
static int plic_ariane_warm_irqchip_init(int m_cntx_id, int s_cntx_id)
{
int ret;
/* By default, enable all IRQs for M-mode of target HART */
if (m_cntx_id > -1) {
ret = plic_context_init(&plic, m_cntx_id, true, 0x1);
if (ret)
return ret;
}
/* Enable all IRQs for S-mode of target HART */
if (s_cntx_id > -1) {
ret = plic_context_init(&plic, s_cntx_id, true, 0x0);
if (ret)
return ret;
}
return 0;
}
/*
* Initialize the ariane interrupt controller for current HART.
*/
@@ -127,7 +107,8 @@ static int ariane_irqchip_init(bool cold_boot)
if (ret)
return ret;
}
return plic_ariane_warm_irqchip_init(2 * hartid, 2 * hartid + 1);
return plic_warm_irqchip_init(&plic, 2 * hartid, 2 * hartid + 1);
}
/*

25
platform/fpga/openpiton/platform.c
View File

@@ -43,6 +43,7 @@ static struct plic_data plic = {
.addr = OPENPITON_DEFAULT_PLIC_ADDR,
.size = OPENPITON_DEFAULT_PLIC_SIZE,
.num_src = OPENPITON_DEFAULT_PLIC_NUM_SOURCES,
.flags = PLIC_FLAG_ARIANE_BUG,
};
static struct aclint_mswi_data mswi = {
@@ -124,27 +125,6 @@ static int openpiton_final_init(bool cold_boot)
return 0;
}
static int plic_openpiton_warm_irqchip_init(int m_cntx_id, int s_cntx_id)
{
int ret;
/* By default, enable all IRQs for M-mode of target HART */
if (m_cntx_id > -1) {
ret = plic_context_init(&plic, m_cntx_id, true, 0x1);
if (ret)
return ret;
}
/* Enable all IRQs for S-mode of target HART */
if (s_cntx_id > -1) {
ret = plic_context_init(&plic, s_cntx_id, true, 0x0);
if (ret)
return ret;
}
return 0;
}
/*
* Initialize the openpiton interrupt controller for current HART.
*/
@@ -158,7 +138,8 @@ static int openpiton_irqchip_init(bool cold_boot)
if (ret)
return ret;
}
return plic_openpiton_warm_irqchip_init(2 * hartid, 2 * hartid + 1);
return plic_warm_irqchip_init(&plic, 2 * hartid, 2 * hartid + 1);
}
/*