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lib: utils/irqchip: plic: Allow enabling IRQs by default

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Unlike other platforms, Ariane and OpenPiton enable all IRQs by default.
This was described in commit b44e844880 ("Add support for Ariane FPGA
SoC") as "due to some issue of the design." Add this workaround behind a
flag in plic_warm_irqchip_init(), so every platform can use the same
warm init function.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Samuel Holland
2024-11-04 20:10:02 -08:00
committed by Anup Patel
parent 86d2c1797a
commit a786aed08d
4 changed files with 21 additions and 53 deletions
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17
lib/utils/irqchip/plic.c
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@@ -121,8 +121,8 @@ void plic_context_restore(const struct plic_data *plic, int context_id,
plic_set_thresh(plic, context_id, threshold);
}
int plic_context_init(const struct plic_data *plic, int context_id,
bool enable, u32 threshold)
static int plic_context_init(const struct plic_data *plic, int context_id,
bool enable, u32 threshold)
{
u32 ie_words, ie_value;
@@ -143,18 +143,23 @@ int plic_context_init(const struct plic_data *plic, int context_id,
int plic_warm_irqchip_init(const struct plic_data *plic,
int m_cntx_id, int s_cntx_id)
{
bool enable;
int ret;
/* By default, disable all IRQs for M-mode of target HART */
/*
* By default, disable all IRQs for the target HART. Ariane
* has a bug which requires enabling all interrupts at boot.
*/
enable = plic->flags & PLIC_FLAG_ARIANE_BUG;
if (m_cntx_id > -1) {
ret = plic_context_init(plic, m_cntx_id, false, 0x7);
ret = plic_context_init(plic, m_cntx_id, enable, 0x7);
if (ret)
return ret;
}
/* By default, disable all IRQs for S-mode of target HART */
if (s_cntx_id > -1) {
ret = plic_context_init(plic, s_cntx_id, false, 0x7);
ret = plic_context_init(plic, s_cntx_id, enable, 0x7);
if (ret)
return ret;
}