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sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device

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Add support for custom PMU extensions to set inhibit bits
on custom CSRs by introducing the PMU device callback
hw_counter_filter_mode(). This allows the perf tool to
restrict event counting under a specified privileged
mode by appending a modifier, e.g. perf record -e event:k
to count events only happening in kernel mode.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Yu Chien Peter Lin
2023-11-30 20:42:02 +08:00
committed by Anup Patel
parent 090fa99d7c
commit a48f2cfd94
2 changed files with 20 additions and 6 deletions
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6
include/sbi/sbi_pmu.h
View File

@@ -89,6 +89,12 @@ struct sbi_pmu_device {
* Custom function returning the machine-specific irq-bit. * Custom function returning the machine-specific irq-bit.
*/ */
int (*hw_counter_irq_bit)(void); int (*hw_counter_irq_bit)(void);
/**
* Custom function to inhibit counting of events while in
* specified mode.
*/
void (*hw_counter_filter_mode)(unsigned long flags, int counter_index);
}; };
/** Get the PMU platform device */ /** Get the PMU platform device */

20
lib/sbi/sbi_pmu.c
View File

@@ -599,7 +599,10 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx,
pmu_dev->hw_counter_disable_irq(ctr_idx); pmu_dev->hw_counter_disable_irq(ctr_idx);
/* Update the inhibit flags based on inhibit flags received from supervisor */ /* Update the inhibit flags based on inhibit flags received from supervisor */
pmu_update_inhibit_flags(flags, &mhpmevent_val); if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
pmu_update_inhibit_flags(flags, &mhpmevent_val);
if (pmu_dev && pmu_dev->hw_counter_filter_mode)
pmu_dev->hw_counter_filter_mode(flags, ctr_idx);
#if __riscv_xlen == 32 #if __riscv_xlen == 32
csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF); csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF);
@@ -620,7 +623,8 @@ static int pmu_fixed_ctr_update_inhibit_bits(int fixed_ctr, unsigned long flags)
#if __riscv_xlen == 32 #if __riscv_xlen == 32
uint64_t cfgh_csr_no; uint64_t cfgh_csr_no;
#endif #endif
if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF)) if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF) &&
!(pmu_dev && pmu_dev->hw_counter_filter_mode))
return fixed_ctr; return fixed_ctr;
switch (fixed_ctr) { switch (fixed_ctr) {
@@ -641,13 +645,17 @@ static int pmu_fixed_ctr_update_inhibit_bits(int fixed_ctr, unsigned long flags)
} }
cfg_val |= MHPMEVENT_MINH; cfg_val |= MHPMEVENT_MINH;
pmu_update_inhibit_flags(flags, &cfg_val); if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF)) {
pmu_update_inhibit_flags(flags, &cfg_val);
#if __riscv_xlen == 32 #if __riscv_xlen == 32
csr_write_num(cfg_csr_no, cfg_val & 0xFFFFFFFF); csr_write_num(cfg_csr_no, cfg_val & 0xFFFFFFFF);
csr_write_num(cfgh_csr_no, cfg_val >> BITS_PER_LONG); csr_write_num(cfgh_csr_no, cfg_val >> BITS_PER_LONG);
#else #else
csr_write_num(cfg_csr_no, cfg_val); csr_write_num(cfg_csr_no, cfg_val);
#endif #endif
}
if (pmu_dev && pmu_dev->hw_counter_filter_mode)
pmu_dev->hw_counter_filter_mode(flags, fixed_ctr);
return fixed_ctr; return fixed_ctr;
} }