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platform: Add HSM implementation for Allwinner D1

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Allwinner D1 contains a "PPU" power domain controller which can
automatically power down/up the CPU power domain. This power domain
includes the C906 core along with its CLINT and PLIC.

This HSM implementation supports non-retentive hart suspend by:
  1) Saving/restoring state that is lost during hart suspend,
  2) Performing cache maintenance before/after hart suspend,
  3) Configuring wakeup sources before hart suspend, and
  4) Asking the PPU to power down the hart when it enters WFI.

Since this HSM implementation is for a single-core SoC, it does not need
to worry about concurrency or saving multiple instances of state.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Samuel Holland
2022-06-12 20:03:55 -05:00
committed by Anup Patel
parent 5e5675874c
commit 9dc5ec5c51
2 changed files with 216 additions and 0 deletions
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6
platform/generic/allwinner/objects.mk Normal file
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#
# SPDX-License-Identifier: BSD-2-Clause
#
carray-platform_override_modules-y += sun20i_d1
platform-objs-y += allwinner/sun20i-d1.o