Firmware/opensbi
8
0
Fork 0
forked from Mirrors/opensbi
Code Pull Requests Activity

lib: utils: atcsmu: Add Andes System Management Unit support

Browse Source 
This patch adds atcsmu support for Andes AE350 platforms. The SMU
provides system management capabilities, including clock, reset
and power control based on power domain partitions.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Yu Chien Peter Lin
2023-01-20 11:05:10 +08:00
committed by Anup Patel
parent b1818ee244
commit 9c4eb3521e
5 changed files with 157 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

92
lib/utils/sys/atcsmu.c Normal file
View File

@@ -0,0 +1,92 @@
/*
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2023 Andes Technology Corporation
*
* Authors:
* Yu Chien Peter Lin <peterlin@andestech.com>
*/
#include <sbi_utils/sys/atcsmu.h>
#include <sbi/riscv_io.h>
#include <sbi/sbi_console.h>
#include <sbi/sbi_error.h>
#include <sbi/sbi_bitops.h>
inline int smu_set_wakeup_events(struct smu_data *smu, u32 events, u32 hartid)
{
if (smu) {
writel(events, (void *)(smu->addr + PCSm_WE_OFFSET(hartid)));
return 0;
} else
return SBI_EINVAL;
}
inline bool smu_support_sleep_mode(struct smu_data *smu, u32 sleep_mode,
u32 hartid)
{
u32 pcs_cfg;
if (!smu) {
sbi_printf("%s(): Failed to access smu_data\n", __func__);
return false;
}
pcs_cfg = readl((void *)(smu->addr + PCSm_CFG_OFFSET(hartid)));
switch (sleep_mode) {
case LIGHTSLEEP_MODE:
if (EXTRACT_FIELD(pcs_cfg, PCS_CFG_LIGHT_SLEEP) == 0) {
sbi_printf(
"SMU: hart%d (PCS%d) does not support light sleep mode\n",
hartid, hartid + 3);
return false;
}
break;
case DEEPSLEEP_MODE:
if (EXTRACT_FIELD(pcs_cfg, PCS_CFG_DEEP_SLEEP) == 0) {
sbi_printf(
"SMU: hart%d (PCS%d) does not support deep sleep mode\n",
hartid, hartid + 3);
return false;
}
break;
}
return true;
}
inline int smu_set_command(struct smu_data *smu, u32 pcs_ctl, u32 hartid)
{
if (smu) {
writel(pcs_ctl, (void *)(smu->addr + PCSm_CTL_OFFSET(hartid)));
return 0;
} else
return SBI_EINVAL;
}
inline int smu_set_reset_vector(struct smu_data *smu, ulong wakeup_addr,
u32 hartid)
{
u32 vec_lo, vec_hi;
u64 reset_vector;
if (!smu)
return SBI_EINVAL;
writel(wakeup_addr, (void *)(smu->addr + HARTn_RESET_VEC_LO(hartid)));
writel((u64)wakeup_addr >> 32,
(void *)(smu->addr + HARTn_RESET_VEC_HI(hartid)));
vec_lo = readl((void *)(smu->addr + HARTn_RESET_VEC_LO(hartid)));
vec_hi = readl((void *)(smu->addr + HARTn_RESET_VEC_HI(hartid)));
reset_vector = ((u64)vec_hi << 32) | vec_lo;
if (reset_vector != (u64)wakeup_addr) {
sbi_printf(
"hard%d (PCS%d): Failed to program the reset vector.\n",
hartid, hartid + 3);
return SBI_EFAIL;
} else
return 0;
}