Firmware/opensbi
8
0
Fork 0
forked from Mirrors/opensbi
Code Pull Requests Activity

lib: sbi: Set the scratch allocation to alignment to cacheline size

Browse Source 
Set the scratch allocation alignment to cacheline size specified by
riscv,cbom-block-size in the DTS file to avoid two atomic variables
from the same cache line causing livelock on some platforms. If the
cacheline is not specified, we set it a default value.

Signed-off-by: Raj Vishwanathan <Raj.Vishwanathan@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20250423225045.267983-1-Raj.Vishwanathan@gmail.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Raj Vishwanathan
2025-04-23 15:50:45 -07:00
committed by Anup Patel
parent 4d0128ec58
commit 99aabc6b84
5 changed files with 63 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
platform/generic/platform.c
View File

@@ -147,6 +147,8 @@ unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
const void *fdt = (void *)arg1;
u32 hartid, hart_count = 0;
int rc, root_offset, cpus_offset, cpu_offset, len;
unsigned long cbom_block_size = 0;
unsigned long tmp = 0;
root_offset = fdt_path_offset(fdt, "/");
if (root_offset < 0)
@@ -174,11 +176,17 @@ unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
continue;
generic_hart_index2id[hart_count++] = hartid;
rc = fdt_parse_cbom_block_size(fdt, cpu_offset, &tmp);
if (rc)
continue;
cbom_block_size = MAX(tmp, cbom_block_size);
}
platform.hart_count = hart_count;
platform.heap_size = fw_platform_get_heap_size(fdt, hart_count);
platform_has_mlevel_imsic = fdt_check_imsic_mlevel(fdt);
platform.cbom_block_size = cbom_block_size;
fw_platform_coldboot_harts_init(fdt);