forked from Mirrors/opensbi
lib: Add hfence instruction encoding
Currently, the toolchains do not have support for hfence instruction. Hence, the instruction are hardcode until we have toolchain support. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
75
lib/sbi/sbi_hfence.S
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75
lib/sbi/sbi_hfence.S
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@@ -0,0 +1,75 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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* Atish Patra <anup.patel@wdc.com>
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*/
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/*
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* Instruction encoding of hfence.gvma is:
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* 0110001 rs2(5) rs1(5) 000 00000 1110011
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*/
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.align 3
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.global __sbi_hfence_gvma_vmid_gpa
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__sbi_hfence_gvma_vmid_gpa:
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/* hfence.gvma a1, a0 */
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.word 0x62a60073
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ret
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.align 3
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.global __sbi_hfence_gvma_vmid
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__sbi_hfence_gvma_vmid:
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/* hfence.gvma zero, a0 */
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.word 0x62a00073
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ret
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.align 3
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.global __sbi_hfence_gvma_gpa
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__sbi_hfence_gvma_gpa:
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/* hfence.gvma a0 */
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.word 0x62050073
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ret
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.align 3
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.global __sbi_hfence_gvma_all
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__sbi_hfence_gvma_all:
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/* hfence.gvma */
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.word 0x62000073
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ret
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/*
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* Instruction encoding of hfence.bvma is:
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* 0010001 rs2(5) rs1(5) 000 00000 1110011
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*/
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.align 3
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.global __sbi_hfence_vvma_asid_va
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__sbi_hfence_vvma_asid_va:
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/* hfence.bvma a1, a0 */
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.word 0x22a60073
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ret
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.align 3
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.global __sbi_hfence_vvma_asid
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__sbi_hfence_vvma_asid:
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/* hfence.bvma zero, a0 */
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.word 0x22a00073
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ret
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.align 3
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.global __sbi_hfence_vvma_va
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__sbi_hfence_vvma_va:
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/* hfence.bvma a0 */
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.word 0x22050073
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ret
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.align 3
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.global __sbi_hfence_vvma_all
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__sbi_hfence_vvma_all:
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/* hfence.bvma */
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.word 0x22000073
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ret
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