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lib: sbi: change prototype of sbi_misaligned_load/store_handler

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This simplifies both handlers such that when the handler needs to
redirect the original trap, it's readily available.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Bo Gan
2024-03-05 18:35:37 -08:00
committed by Anup Patel
parent a17600c186
commit 9221fe58d1
3 changed files with 35 additions and 45 deletions
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9
include/sbi/sbi_trap_ldst.h
View File

@@ -11,13 +11,14 @@
#define __SBI_TRAP_LDST_H__ #define __SBI_TRAP_LDST_H__
#include <sbi/sbi_types.h> #include <sbi/sbi_types.h>
#include <sbi/sbi_trap.h>
struct sbi_trap_regs; struct sbi_trap_regs;
int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst, int sbi_misaligned_load_handler(struct sbi_trap_regs *regs,
struct sbi_trap_regs *regs); const struct sbi_trap_info *orig_trap);
int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst, int sbi_misaligned_store_handler(struct sbi_trap_regs *regs,
struct sbi_trap_regs *regs); const struct sbi_trap_info *orig_trap);
#endif #endif

21
lib/sbi/sbi_trap.c
View File

@@ -285,6 +285,13 @@ struct sbi_trap_regs *sbi_trap_handler(struct sbi_trap_regs *regs)
} }
return regs; return regs;
} }
/* Original trap_info */
trap.epc = regs->mepc;
trap.cause = mcause;
trap.tval = mtval;
trap.tval2 = mtval2;
trap.tinst = mtinst;
trap.gva = sbi_regs_gva(regs);
switch (mcause) { switch (mcause) {
case CAUSE_ILLEGAL_INSTRUCTION: case CAUSE_ILLEGAL_INSTRUCTION:
@@ -292,11 +299,11 @@ struct sbi_trap_regs *sbi_trap_handler(struct sbi_trap_regs *regs)
msg = "illegal instruction handler failed"; msg = "illegal instruction handler failed";
break; break;
case CAUSE_MISALIGNED_LOAD: case CAUSE_MISALIGNED_LOAD:
rc = sbi_misaligned_load_handler(mtval, mtval2, mtinst, regs); rc = sbi_misaligned_load_handler(regs, &trap);
msg = "misaligned load handler failed"; msg = "misaligned load handler failed";
break; break;
case CAUSE_MISALIGNED_STORE: case CAUSE_MISALIGNED_STORE:
rc = sbi_misaligned_store_handler(mtval, mtval2, mtinst, regs); rc = sbi_misaligned_store_handler(regs, &trap);
msg = "misaligned store handler failed"; msg = "misaligned store handler failed";
break; break;
case CAUSE_SUPERVISOR_ECALL: case CAUSE_SUPERVISOR_ECALL:
@@ -311,14 +318,8 @@ struct sbi_trap_regs *sbi_trap_handler(struct sbi_trap_regs *regs)
/* fallthrough */ /* fallthrough */
default: default:
/* If the trap came from S or U mode, redirect it there */ /* If the trap came from S or U mode, redirect it there */
trap.epc = regs->mepc; msg = "trap redirect failed";
trap.cause = mcause; rc = sbi_trap_redirect(regs, &trap);
trap.tval = mtval;
trap.tval2 = mtval2;
trap.tinst = mtinst;
trap.gva = sbi_regs_gva(regs);
rc = sbi_trap_redirect(regs, &trap);
break; break;
} }

50
lib/sbi/sbi_trap_ldst.c
View File

@@ -34,8 +34,8 @@ static ulong sbi_misaligned_tinst_fixup(ulong orig_tinst, ulong new_tinst,
return orig_tinst | (addr_offset << SH_RS1); return orig_tinst | (addr_offset << SH_RS1);
} }
int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst, int sbi_misaligned_load_handler(struct sbi_trap_regs *regs,
struct sbi_trap_regs *regs) const struct sbi_trap_info *orig_trap)
{ {
ulong insn, insn_len; ulong insn, insn_len;
union reg_data val; union reg_data val;
@@ -44,13 +44,13 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
sbi_pmu_ctr_incr_fw(SBI_PMU_FW_MISALIGNED_LOAD); sbi_pmu_ctr_incr_fw(SBI_PMU_FW_MISALIGNED_LOAD);
if (tinst & 0x1) { if (orig_trap->tinst & 0x1) {
/* /*
* Bit[0] == 1 implies trapped instruction value is * Bit[0] == 1 implies trapped instruction value is
* transformed instruction or custom instruction. * transformed instruction or custom instruction.
*/ */
insn = tinst | INSN_16BIT_MASK; insn = orig_trap->tinst | INSN_16BIT_MASK;
insn_len = (tinst & 0x2) ? INSN_LEN(insn) : 2; insn_len = (orig_trap->tinst & 0x2) ? INSN_LEN(insn) : 2;
} else { } else {
/* /*
* Bit[0] == 0 implies trapped instruction value is * Bit[0] == 0 implies trapped instruction value is
@@ -131,23 +131,17 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
shift = 8 * (sizeof(ulong) - len); shift = 8 * (sizeof(ulong) - len);
insn = RVC_RS2S(insn) << SH_RD; insn = RVC_RS2S(insn) << SH_RD;
} else { } else {
uptrap.epc = regs->mepc; return sbi_trap_redirect(regs, orig_trap);
uptrap.cause = CAUSE_MISALIGNED_LOAD;
uptrap.tval = addr;
uptrap.tval2 = tval2;
uptrap.tinst = tinst;
uptrap.gva = sbi_regs_gva(regs);
return sbi_trap_redirect(regs, &uptrap);
} }
val.data_u64 = 0; val.data_u64 = 0;
for (i = 0; i < len; i++) { for (i = 0; i < len; i++) {
val.data_bytes[i] = sbi_load_u8((void *)(addr + i), val.data_bytes[i] =
&uptrap); sbi_load_u8((void *)(orig_trap->tval + i), &uptrap);
if (uptrap.cause) { if (uptrap.cause) {
uptrap.epc = regs->mepc; uptrap.epc = regs->mepc;
uptrap.tinst = sbi_misaligned_tinst_fixup( uptrap.tinst = sbi_misaligned_tinst_fixup(
tinst, uptrap.tinst, i); orig_trap->tinst, uptrap.tinst, i);
return sbi_trap_redirect(regs, &uptrap); return sbi_trap_redirect(regs, &uptrap);
} }
} }
@@ -166,8 +160,8 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
return 0; return 0;
} }
int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst, int sbi_misaligned_store_handler(struct sbi_trap_regs *regs,
struct sbi_trap_regs *regs) const struct sbi_trap_info *orig_trap)
{ {
ulong insn, insn_len; ulong insn, insn_len;
union reg_data val; union reg_data val;
@@ -176,13 +170,13 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
sbi_pmu_ctr_incr_fw(SBI_PMU_FW_MISALIGNED_STORE); sbi_pmu_ctr_incr_fw(SBI_PMU_FW_MISALIGNED_STORE);
if (tinst & 0x1) { if (orig_trap->tinst & 0x1) {
/* /*
* Bit[0] == 1 implies trapped instruction value is * Bit[0] == 1 implies trapped instruction value is
* transformed instruction or custom instruction. * transformed instruction or custom instruction.
*/ */
insn = tinst | INSN_16BIT_MASK; insn = orig_trap->tinst | INSN_16BIT_MASK;
insn_len = (tinst & 0x2) ? INSN_LEN(insn) : 2; insn_len = (orig_trap->tinst & 0x2) ? INSN_LEN(insn) : 2;
} else { } else {
/* /*
* Bit[0] == 0 implies trapped instruction value is * Bit[0] == 0 implies trapped instruction value is
@@ -248,22 +242,16 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
len = 2; len = 2;
val.data_ulong = GET_RS2S(insn, regs); val.data_ulong = GET_RS2S(insn, regs);
} else { } else {
uptrap.epc = regs->mepc; return sbi_trap_redirect(regs, orig_trap);
uptrap.cause = CAUSE_MISALIGNED_STORE;
uptrap.tval = addr;
uptrap.tval2 = tval2;
uptrap.tinst = tinst;
uptrap.gva = sbi_regs_gva(regs);
return sbi_trap_redirect(regs, &uptrap);
} }
for (i = 0; i < len; i++) { for (i = 0; i < len; i++) {
sbi_store_u8((void *)(addr + i), val.data_bytes[i], sbi_store_u8((void *)(orig_trap->tval + i), val.data_bytes[i],
&uptrap); &uptrap);
if (uptrap.cause) { if (uptrap.cause) {
uptrap.epc = regs->mepc; uptrap.epc = regs->mepc;
uptrap.tinst = sbi_misaligned_tinst_fixup( uptrap.tinst = sbi_misaligned_tinst_fixup(
tinst, uptrap.tinst, i); orig_trap->tinst, uptrap.tinst, i);
return sbi_trap_redirect(regs, &uptrap); return sbi_trap_redirect(regs, &uptrap);
} }
} }