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lib: irqchip/plic: Factor out a context init function

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This simplifies both the callers and the callees by removing duplicated
code and consolidating the error handling. It also fixes two bugs in the
process:
  1) ie_words was one too large when plic->num_src was a multiple of 32.
  2) plic_set_ie takes a 32-bit mask, not a Boolean value, so the FPGA
     platforms previously only enabled one out of every 32 interrupts.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Samuel Holland
2022-06-12 20:03:50 -05:00
committed by Anup Patel
parent 2ea7799d56
commit 8c362e7d06
4 changed files with 49 additions and 54 deletions
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8
include/sbi_utils/irqchip/plic.h
View File

@@ -17,14 +17,12 @@ struct plic_data {
unsigned long num_src;
};
int plic_context_init(const struct plic_data *plic, int context_id,
bool enable, u32 threshold);
int plic_warm_irqchip_init(const struct plic_data *plic,
int m_cntx_id, int s_cntx_id);
int plic_cold_irqchip_init(const struct plic_data *plic);
void plic_set_thresh(const struct plic_data *plic, u32 cntxid, u32 val);
void plic_set_ie(const struct plic_data *plic, u32 cntxid,
u32 word_index, u32 val);
#endif

55
lib/utils/irqchip/plic.c
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@@ -5,6 +5,7 @@
*
* Authors:
* Anup Patel <anup.patel@wdc.com>
* Samuel Holland <samuel@sholland.org>
*/
#include <sbi/riscv_io.h>
@@ -28,61 +29,63 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
writel(val, plic_priority);
}
void plic_set_thresh(const struct plic_data *plic, u32 cntxid, u32 val)
static void plic_set_thresh(const struct plic_data *plic, u32 cntxid, u32 val)
{
volatile void *plic_thresh;
if (!plic)
return;
plic_thresh = (char *)plic->addr +
PLIC_CONTEXT_BASE + PLIC_CONTEXT_STRIDE * cntxid;
writel(val, plic_thresh);
}
void plic_set_ie(const struct plic_data *plic, u32 cntxid,
static void plic_set_ie(const struct plic_data *plic, u32 cntxid,
u32 word_index, u32 val)
{
volatile char *plic_ie;
if (!plic)
return;
plic_ie = (char *)plic->addr +
PLIC_ENABLE_BASE + PLIC_ENABLE_STRIDE * cntxid;
writel(val, plic_ie + word_index * 4);
}
int plic_context_init(const struct plic_data *plic, int context_id,
bool enable, u32 threshold)
{
u32 ie_words, ie_value;
if (!plic || context_id < 0)
return SBI_EINVAL;
ie_words = (plic->num_src + 31) / 32;
ie_value = enable ? 0xffffffffU : 0U;
for (u32 i = 0; i < ie_words; i++)
plic_set_ie(plic, context_id, i, ie_value);
plic_set_thresh(plic, context_id, threshold);
return 0;
}
int plic_warm_irqchip_init(const struct plic_data *plic,
int m_cntx_id, int s_cntx_id)
{
size_t i, ie_words;
if (!plic)
return SBI_EINVAL;
ie_words = plic->num_src / 32 + 1;
int ret;
/* By default, disable all IRQs for M-mode of target HART */
if (m_cntx_id > -1) {
for (i = 0; i < ie_words; i++)
plic_set_ie(plic, m_cntx_id, i, 0);
ret = plic_context_init(plic, m_cntx_id, false, 0x7);
if (ret)
return ret;
}
/* By default, disable all IRQs for S-mode of target HART */
if (s_cntx_id > -1) {
for (i = 0; i < ie_words; i++)
plic_set_ie(plic, s_cntx_id, i, 0);
ret = plic_context_init(plic, m_cntx_id, false, 0x7);
if (ret)
return ret;
}
/* By default, disable M-mode threshold */
if (m_cntx_id > -1)
plic_set_thresh(plic, m_cntx_id, 0x7);
/* By default, disable S-mode threshold */
if (s_cntx_id > -1)
plic_set_thresh(plic, s_cntx_id, 0x7);
return 0;
}

19
platform/fpga/ariane/platform.c
View File

@@ -99,24 +99,21 @@ static int ariane_console_init(void)
static int plic_ariane_warm_irqchip_init(int m_cntx_id, int s_cntx_id)
{
size_t i, ie_words = ARIANE_PLIC_NUM_SOURCES / 32 + 1;
int ret;
/* By default, enable all IRQs for M-mode of target HART */
if (m_cntx_id > -1) {
for (i = 0; i < ie_words; i++)
plic_set_ie(&plic, m_cntx_id, i, 1);
ret = plic_context_init(&plic, m_cntx_id, true, 0x1);
if (ret)
return ret;
}
/* Enable all IRQs for S-mode of target HART */
if (s_cntx_id > -1) {
for (i = 0; i < ie_words; i++)
plic_set_ie(&plic, s_cntx_id, i, 1);
ret = plic_context_init(&plic, s_cntx_id, true, 0x0);
if (ret)
return ret;
}
/* By default, enable M-mode threshold */
if (m_cntx_id > -1)
plic_set_thresh(&plic, m_cntx_id, 1);
/* By default, disable S-mode threshold */
if (s_cntx_id > -1)
plic_set_thresh(&plic, s_cntx_id, 0);
return 0;
}

19
platform/fpga/openpiton/platform.c
View File

@@ -134,24 +134,21 @@ static int openpiton_console_init(void)
static int plic_openpiton_warm_irqchip_init(int m_cntx_id, int s_cntx_id)
{
size_t i, ie_words = plic.num_src / 32 + 1;
int ret;
/* By default, enable all IRQs for M-mode of target HART */
if (m_cntx_id > -1) {
for (i = 0; i < ie_words; i++)
plic_set_ie(&plic, m_cntx_id, i, 1);
ret = plic_context_init(&plic, m_cntx_id, true, 0x1);
if (ret)
return ret;
}
/* Enable all IRQs for S-mode of target HART */
if (s_cntx_id > -1) {
for (i = 0; i < ie_words; i++)
plic_set_ie(&plic, s_cntx_id, i, 1);
ret = plic_context_init(&plic, s_cntx_id, true, 0x0);
if (ret)
return ret;
}
/* By default, enable M-mode threshold */
if (m_cntx_id > -1)
plic_set_thresh(&plic, m_cntx_id, 1);
/* By default, disable S-mode threshold */
if (s_cntx_id > -1)
plic_set_thresh(&plic, s_cntx_id, 0);
return 0;
}