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include: Extend get_insn() to read instruction from VS/VU mode

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Current implementation of get_insn() is not suitable for reading
instruction from VS/VU mode because we have to set SSTATUS_MXR bit
in VSSTATUS CSR for reading instruction from VS/VU mode.

This patch extends get_insn() to read instruction from VS/VU mode.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel
2019-08-17 20:54:40 +05:30
committed by Anup Patel
parent a14e7ee82c
commit 7d4420bd69
4 changed files with 47 additions and 28 deletions
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2
include/sbi/riscv_unpriv.h
View File

@@ -43,7 +43,7 @@ DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64)
DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64)
DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong)
ulong get_insn(ulong mepc, struct sbi_scratch *scratch,
ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
struct unpriv_trap *trap);
#endif

16
lib/sbi/riscv_unpriv.c
View File

@@ -97,20 +97,22 @@ void store_u64(u64 *addr, u64 val,
}
#endif
ulong get_insn(ulong mepc, struct sbi_scratch *scratch,
ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
struct unpriv_trap *trap)
{
ulong __mstatus = 0, val = 0;
ulong __mstatus = 0, __vsstatus = 0, val = 0;
#ifdef __riscv_compressed
ulong rvc_mask = 3, tmp;
#endif
if (trap) {
trap->ilen = 4;
trap->cause = 0;
trap->tval = 0;
sbi_hart_set_trap_info(scratch, trap);
}
if (virt)
__vsstatus = csr_read_set(CSR_VSSTATUS, SSTATUS_MXR);
#ifndef __riscv_compressed
asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
#if __riscv_xlen == 64
@@ -134,7 +136,10 @@ ulong get_insn(ulong mepc, struct sbi_scratch *scratch,
: [mprv] "r"(MSTATUS_MPRV | MSTATUS_MXR), [addr] "r"(mepc),
[rvc_mask] "r"(rvc_mask));
#endif
if (trap) {
if (virt)
csr_write(CSR_VSSTATUS, __vsstatus);
sbi_hart_set_trap_info(scratch, NULL);
switch (trap->cause) {
case CAUSE_LOAD_ACCESS:
@@ -148,7 +153,6 @@ ulong get_insn(ulong mepc, struct sbi_scratch *scratch,
default:
break;
};
}
return val;
}

9
lib/sbi/sbi_illegal_insn.c
View File

@@ -130,12 +130,17 @@ int sbi_illegal_insn_handler(u32 hartid, ulong mcause,
struct sbi_trap_regs *regs,
struct sbi_scratch *scratch)
{
ulong insn = csr_read(mbadaddr);
ulong insn = csr_read(CSR_MTVAL);
#if __riscv_xlen == 32
bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
#else
bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
#endif
struct unpriv_trap uptrap;
if (unlikely((insn & 3) != 3)) {
if (insn == 0) {
insn = get_insn(regs->mepc, scratch, &uptrap);
insn = get_insn(regs->mepc, virt, scratch, &uptrap);
if (uptrap.cause)
return sbi_trap_redirect(regs, scratch,
regs->mepc, uptrap.cause, uptrap.tval);

14
lib/sbi/sbi_misaligned_ldst.c
View File

@@ -27,9 +27,14 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
{
union reg_data val;
struct unpriv_trap uptrap;
ulong insn = get_insn(regs->mepc, scratch, &uptrap);
ulong addr = csr_read(CSR_MTVAL);
int i, fp = 0, shift = 0, len = 0;
#if __riscv_xlen == 32
bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
#else
bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
#endif
ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap);
if (uptrap.cause)
return sbi_trap_redirect(regs, scratch, regs->mepc,
@@ -129,9 +134,14 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
{
union reg_data val;
struct unpriv_trap uptrap;
ulong insn = get_insn(regs->mepc, scratch, &uptrap);
ulong addr = csr_read(CSR_MTVAL);
int i, len = 0;
#if __riscv_xlen == 32
bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
#else
bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
#endif
ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap);
if (uptrap.cause)
return sbi_trap_redirect(regs, scratch, regs->mepc,