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include: Extend get_insn() to read instruction from VS/VU mode

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Current implementation of get_insn() is not suitable for reading
instruction from VS/VU mode because we have to set SSTATUS_MXR bit
in VSSTATUS CSR for reading instruction from VS/VU mode.

This patch extends get_insn() to read instruction from VS/VU mode.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel
2019-08-17 20:54:40 +05:30
committed by Anup Patel
parent a14e7ee82c
commit 7d4420bd69
4 changed files with 47 additions and 28 deletions
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14
lib/sbi/sbi_misaligned_ldst.c
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@@ -27,9 +27,14 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
{
union reg_data val;
struct unpriv_trap uptrap;
ulong insn = get_insn(regs->mepc, scratch, &uptrap);
ulong addr = csr_read(CSR_MTVAL);
int i, fp = 0, shift = 0, len = 0;
#if __riscv_xlen == 32
bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
#else
bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
#endif
ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap);
if (uptrap.cause)
return sbi_trap_redirect(regs, scratch, regs->mepc,
@@ -129,9 +134,14 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
{
union reg_data val;
struct unpriv_trap uptrap;
ulong insn = get_insn(regs->mepc, scratch, &uptrap);
ulong addr = csr_read(CSR_MTVAL);
int i, len = 0;
#if __riscv_xlen == 32
bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
#else
bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
#endif
ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap);
if (uptrap.cause)
return sbi_trap_redirect(regs, scratch, regs->mepc,